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WAW hazards elimination (#2881)
This PR introduces a new RAW hazard detection mechanism to eliminate WAW hazards in CVA6 issue stage. It first checks for hazards in all scoreboard entries in parallel. Then it filters found hazards before vs after the current issue pointer. It then finds the index of the last hazard before (resp. after) the issue pointer. Finally, it gives precedence to a hazard before the issue pointer over the one after the issue pointer. --------- Co-authored-by: Junheng Zheng <junheng.zheng@thalesgroup.com> Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
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parent
eb3ff25f15
commit
c784fd9047
7 changed files with 248 additions and 274 deletions
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@ -1,2 +1,2 @@
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cv32a65x:
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gates: 184679
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gates: 182076
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@ -19,12 +19,12 @@ iterations = None
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# Keep it up-to-date with compiler version and core performance improvements
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# Will fail if the number of cycles is different from this one
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valid_cycles = {
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"dhrystone_dual": 18935,
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"dhrystone_single": 24127,
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"coremark_dual": 1001191,
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"coremark_single": 1300030,
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"dhrystone_cv32a65x": 31976,
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"dhrystone_cv32a60x": 39449,
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"dhrystone_dual": 17159,
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"dhrystone_single": 22407,
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"coremark_dual": 981777,
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"coremark_single": 1294524,
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"dhrystone_cv32a65x": 30056,
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"dhrystone_cv32a60x": 37474,
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}
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for arg in sys.argv[1:]:
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@ -113,6 +113,7 @@ sources:
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- core/ariane_regfile_ff.sv
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- core/ariane_regfile_fpga.sv
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- core/scoreboard.sv
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- core/raw_checker.sv
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- core/store_buffer.sv
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- core/amo_buffer.sv
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- core/store_unit.sv
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@ -95,6 +95,7 @@ core/mmu_sv39x4/ptw_sv39x4.sv
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core/ariane_regfile_ff.sv
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core/re_name.sv
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core/scoreboard.sv
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core/raw_checker.sv
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core/store_buffer.sv
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core/amo_buffer.sv
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core/store_unit.sv
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@ -132,6 +132,7 @@ ${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
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${CVA6_REPO_DIR}/core/ariane_regfile_fpga.sv
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// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
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${CVA6_REPO_DIR}/core/scoreboard.sv
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${CVA6_REPO_DIR}/core/raw_checker.sv
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${CVA6_REPO_DIR}/core/store_buffer.sv
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${CVA6_REPO_DIR}/core/amo_buffer.sv
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${CVA6_REPO_DIR}/core/store_unit.sv
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@ -136,7 +136,7 @@ module issue_read_operands
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logic none, load, store, alu, alu2, ctrl_flow, mult, csr, fpu, fpu_vec, cvxif, accel;
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} fus_busy_t;
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logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_waw, stall_rs1, stall_rs2, stall_rs3;
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logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_rs1, stall_rs2, stall_rs3;
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logic [CVA6Cfg.NrIssuePorts-1:0] fu_busy; // functional unit is busy
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fus_busy_t [CVA6Cfg.NrIssuePorts-1:0] fus_busy; // which functional units are considered busy
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logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack;
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@ -163,37 +163,44 @@ module issue_read_operands
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logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_n, branch_valid_q;
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logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_n, cvxif_valid_q;
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logic [31:0] cvxif_off_instr_n, cvxif_off_instr_q;
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logic cvxif_instruction_valid;
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logic cvxif_instruction_valid;
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//RAW detection
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.TRANS_ID_BITS-1:0] idx_hzd_rs1;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_raw_check;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_has_raw;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_fpr;
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.TRANS_ID_BITS-1:0] idx_hzd_rs2;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_raw_check;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_has_raw;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_fpr;
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.TRANS_ID_BITS-1:0] idx_hzd_rs3;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_raw_check;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_has_raw;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_fpr;
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] rd_list;
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rd_fpr;
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//fwd logic
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logic [CVA6Cfg.NrIssuePorts-1:0] rs1_has_raw;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs2_has_raw;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs3_has_raw;
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0][ CVA6Cfg.XLEN-1:0] fwd_res;
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0] fwd_res_valid;
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs3_fpr;
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rs1_is_not_csr;
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rs2_is_not_csr;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs2_valid;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs3_valid;
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs3;
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_res;
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_res;
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3_res;
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// clobber
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fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr, rd_clobber_fpr;
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logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] gpr_clobber_vld;
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logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] fpr_clobber_vld;
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ariane_pkg::fu_t [ CVA6Cfg.NR_SB_ENTRIES:0] clobber_fu;
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//forward logic
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0]
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rs1_fwd_req, rs2_fwd_req, rs3_fwd_req;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs1_is_not_gpr0, rs2_is_not_gpr0, rs3_is_not_gpr0;
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] rs_data;
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logic [CVA6Cfg.NrIssuePorts-1:0] rs1_available, rs2_available, rs3_available;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_valid;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_valid;
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logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_valid;
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs1_res;
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs2_res;
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logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs3_res;
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logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_n, tinst_q; // transformed instruction
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@ -246,7 +253,7 @@ module issue_read_operands
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// TODO check only for 1st instruction ??
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// Allow a cvxif transaction if we WaW condition are ok.
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assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF) && !stall_waw[0];
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assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF);
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assign cvxif_instruction_valid = !issue_instr_i[0].ex.valid && issue_instr_valid_i[0] && cvxif_req_allowed;
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assign x_transaction_accepted_o = x_issue_valid_o && x_issue_ready_i && x_issue_resp_i.accept;
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assign x_transaction_rejected = x_issue_valid_o && x_issue_ready_i && ~x_issue_resp_i.accept;
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@ -408,226 +415,103 @@ module issue_read_operands
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end
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end
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// -------------------
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// RD clobber process
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// -------------------
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// rd_clobber output: output currently clobbered destination registers
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always_comb begin : clobber_assign
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gpr_clobber_vld = '0;
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fpr_clobber_vld = '0;
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// default (highest entry hast lowest prio in arbiter tree below)
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clobber_fu[CVA6Cfg.NR_SB_ENTRIES] = ariane_pkg::NONE;
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for (int unsigned i = 0; i < 2 ** ariane_pkg::REG_ADDR_SIZE; i++) begin
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gpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1;
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fpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1;
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end
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// check for all valid entries and set the clobber accordingly
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for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
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gpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & ~(CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[i].op));
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fpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[i].op));
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clobber_fu[i] = fwd_i.sbe[i].fu;
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end
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// GPR[0] is always free
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gpr_clobber_vld[0] = '0;
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for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
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assign rs1_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(issue_instr_i[i].op));
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assign rs2_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(issue_instr_i[i].op));
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assign rs3_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(issue_instr_i[i].op));
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end
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for (genvar k = 0; k < 2 ** ariane_pkg::REG_ADDR_SIZE; k++) begin : gen_sel_clobbers
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// get fu that is going to clobber this register (there should be only one)
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rr_arb_tree #(
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.NumIn(CVA6Cfg.NR_SB_ENTRIES + 1),
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.DataType(ariane_pkg::fu_t),
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.ExtPrio(1'b1),
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.AxiVldRdy(1'b1)
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) i_sel_gpr_clobbers (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i(1'b0),
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.rr_i ('0),
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.req_i (gpr_clobber_vld[k]),
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.gnt_o (),
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.data_i (clobber_fu),
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.gnt_i (1'b1),
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.req_o (),
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.data_o (rd_clobber_gpr[k]),
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.idx_o ()
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// ----------------------------------
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// Renaming
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// ----------------------------------
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for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
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assign rd_list[i] = fwd_i.sbe[i].rd;
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assign rd_fpr[i] = CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(fwd_i.sbe[i].op);
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end
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for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin : gen_raw_checks
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raw_checker #(
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.CVA6Cfg(CVA6Cfg)
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) i_rs1_last_raw (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.rs_i(issue_instr_i[i].rs1),
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.rs_fpr_i(rs1_fpr[i]),
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.rd_i(rd_list),
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.rd_fpr_i(rd_fpr),
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.still_issued_i(fwd_i.still_issued),
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.issue_pointer_i(fwd_i.issue_pointer),
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.idx_o(idx_hzd_rs1[i]),
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.valid_o(rs1_raw_check[i])
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);
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if (CVA6Cfg.FpPresent) begin
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rr_arb_tree #(
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.NumIn(CVA6Cfg.NR_SB_ENTRIES + 1),
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.DataType(ariane_pkg::fu_t),
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.ExtPrio(1'b1),
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.AxiVldRdy(1'b1)
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) i_sel_fpr_clobbers (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i(1'b0),
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.rr_i ('0),
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.req_i (fpr_clobber_vld[k]),
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.gnt_o (),
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.data_i (clobber_fu),
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.gnt_i (1'b1),
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.req_o (),
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.data_o (rd_clobber_fpr[k]),
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.idx_o ()
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);
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end else begin
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assign rd_clobber_fpr[k] = NONE;
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end
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assign rs1_has_raw[i] = rs1_raw_check[i] && !issue_instr_i[i].use_zimm;
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raw_checker #(
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.CVA6Cfg(CVA6Cfg)
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) i_rs2_last_raw (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.rs_i(issue_instr_i[i].rs2),
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.rs_fpr_i(rs2_fpr[i]),
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.rd_i(rd_list),
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.rd_fpr_i(rd_fpr),
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.still_issued_i(fwd_i.still_issued),
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.issue_pointer_i(fwd_i.issue_pointer),
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.idx_o(idx_hzd_rs2[i]),
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.valid_o(rs2_raw_check[i])
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);
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assign rs2_has_raw[i] = rs2_raw_check[i];
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raw_checker #(
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.CVA6Cfg(CVA6Cfg)
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) i_rs3_last_raw (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.rs_i(issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]),
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.rs_fpr_i(rs3_fpr[i]),
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.rd_i(rd_list),
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.rd_fpr_i(rd_fpr),
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.still_issued_i(fwd_i.still_issued),
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.issue_pointer_i(fwd_i.issue_pointer),
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.idx_o(idx_hzd_rs3[i]),
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.valid_o(rs3_raw_check[i])
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);
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assign rs3_has_raw[i] = rs3_raw_check[i] && rs3_fpr[i];
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end
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// ----------------------------------
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// Read Operands (a.k.a forwarding)
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// ----------------------------------
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// read operand interface: same logic as register file
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always_comb begin
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for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
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fwd_res[i] = fwd_i.sbe[i].result;
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fwd_res_valid[i] = fwd_i.sbe[i].valid;
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end
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for (int unsigned i = 0; i < CVA6Cfg.NrWbPorts; i++) begin
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if (fwd_i.wb[i].valid && !fwd_i.wb[i].ex_valid) begin
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fwd_res[fwd_i.wb[i].trans_id] = fwd_i.wb[i].data;
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fwd_res_valid[fwd_i.wb[i].trans_id] = 1'b1;
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end
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end
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end
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// WB ports have higher prio than entries
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for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
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for (genvar k = 0; unsigned'(k) < CVA6Cfg.NrWbPorts; k++) begin : gen_rs_wb
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assign rs1_res[i] = fwd_res[idx_hzd_rs1[i]];
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assign rs1_is_not_csr[i] = rs1_fpr[i] || (fwd_i.sbe[idx_hzd_rs1[i]].fu != ariane_pkg::CSR) || (CVA6Cfg.RVS && issue_instr_i[i].op == ariane_pkg::SFENCE_VMA);
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assign rs1_valid[i] = fwd_res_valid[idx_hzd_rs1[i]] && rs1_is_not_csr[i];
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assign rs1_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs1) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[fwd_i.wb[k].trans_id].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
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issue_instr_i[i].op
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)));
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assign rs2_res[i] = fwd_res[idx_hzd_rs2[i]];
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assign rs2_is_not_csr[i] = rs2_fpr[i] || (fwd_i.sbe[idx_hzd_rs2[i]].fu != ariane_pkg::CSR) || (CVA6Cfg.RVS && issue_instr_i[i].op == ariane_pkg::SFENCE_VMA);
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assign rs2_valid[i] = fwd_res_valid[idx_hzd_rs2[i]] && rs2_is_not_csr[i];
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|
||||
assign rs2_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs2) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
fwd_i.sbe[fwd_i.wb[k].trans_id].op
|
||||
)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(
|
||||
issue_instr_i[i].op
|
||||
)));
|
||||
assign rs3[i] = fwd_res[idx_hzd_rs3[i]];
|
||||
assign rs3_valid[i] = fwd_res_valid[idx_hzd_rs3[i]];
|
||||
|
||||
assign rs3_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
fwd_i.sbe[fwd_i.wb[k].trans_id].op
|
||||
)) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(
|
||||
issue_instr_i[i].op
|
||||
)));
|
||||
|
||||
assign rs_data[i][k] = fwd_i.wb[k].data;
|
||||
end
|
||||
|
||||
for (genvar k = 0; unsigned'(k) < CVA6Cfg.NR_SB_ENTRIES; k++) begin : gen_rs_entries
|
||||
|
||||
assign rs1_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs1) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
fwd_i.sbe[k].op
|
||||
)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
|
||||
issue_instr_i[i].op
|
||||
)));
|
||||
|
||||
assign rs2_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs2) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
fwd_i.sbe[k].op
|
||||
)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(
|
||||
issue_instr_i[i].op
|
||||
)));
|
||||
|
||||
assign rs3_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
fwd_i.sbe[k].op
|
||||
)) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(
|
||||
issue_instr_i[i].op
|
||||
)));
|
||||
|
||||
assign rs_data[i][k+CVA6Cfg.NrWbPorts] = fwd_i.sbe[k].result;
|
||||
end
|
||||
|
||||
// use fixed prio here
|
||||
// this implicitly gives higher prio to WB ports
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
|
||||
.DataWidth(CVA6Cfg.XLEN),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_sel_rs1 (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.flush_i(1'b0),
|
||||
.rr_i ('0),
|
||||
.req_i (rs1_fwd_req[i]),
|
||||
.gnt_o (),
|
||||
.data_i (rs_data[i]),
|
||||
.gnt_i (1'b1),
|
||||
.req_o (rs1_available[i]),
|
||||
.data_o (rs1_res[i]),
|
||||
.idx_o ()
|
||||
);
|
||||
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
|
||||
.DataWidth(CVA6Cfg.XLEN),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_sel_rs2 (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.flush_i(1'b0),
|
||||
.rr_i ('0),
|
||||
.req_i (rs2_fwd_req[i]),
|
||||
.gnt_o (),
|
||||
.data_i (rs_data[i]),
|
||||
.gnt_i (1'b1),
|
||||
.req_o (rs2_available[i]),
|
||||
.data_o (rs2_res[i]),
|
||||
.idx_o ()
|
||||
);
|
||||
|
||||
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
|
||||
.DataWidth(CVA6Cfg.XLEN),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_sel_rs3 (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.flush_i(1'b0),
|
||||
.rr_i ('0),
|
||||
.req_i (rs3_fwd_req[i]),
|
||||
.gnt_o (),
|
||||
.data_i (rs_data[i]),
|
||||
.gnt_i (1'b1),
|
||||
.req_o (rs3_available[i]),
|
||||
.data_o (rs3[i]),
|
||||
.idx_o ()
|
||||
);
|
||||
|
||||
if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_three_port
|
||||
assign rs3_res[i] = rs3[i][riscv::XLEN-1:0];
|
||||
end else begin : gen_fp_three_port
|
||||
if (CVA6Cfg.NrRgprPorts == 3) begin
|
||||
assign rs3_res[i] = rs3[i][CVA6Cfg.XLEN-1:0];
|
||||
end else begin
|
||||
assign rs3_res[i] = rs3[i][CVA6Cfg.FLen-1:0];
|
||||
end
|
||||
|
||||
assign rs1_has_raw[i] = !issue_instr_i[i].use_zimm && ((CVA6Cfg.FpPresent && is_rs1_fpr(
|
||||
issue_instr_i[i].op
|
||||
)) ? rd_clobber_fpr[issue_instr_i[i].rs1] != NONE :
|
||||
rd_clobber_gpr[issue_instr_i[i].rs1] != NONE);
|
||||
|
||||
assign rs1_valid[i] = rs1_available[i] && (CVA6Cfg.FpPresent && is_rs1_fpr(
|
||||
issue_instr_i[i].op
|
||||
) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs1] != CSR) ||
|
||||
(CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA)));
|
||||
|
||||
assign rs2_has_raw[i] = ((CVA6Cfg.FpPresent && is_rs2_fpr(
|
||||
issue_instr_i[i].op
|
||||
)) ? rd_clobber_fpr[issue_instr_i[i].rs2] != NONE :
|
||||
rd_clobber_gpr[issue_instr_i[i].rs2] != NONE);
|
||||
|
||||
assign rs2_valid[i] = rs2_available[i] && (CVA6Cfg.FpPresent && is_rs2_fpr(
|
||||
issue_instr_i[i].op
|
||||
) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs2] != CSR) ||
|
||||
(CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA)));
|
||||
|
||||
assign rs3_has_raw[i] = ((CVA6Cfg.FpPresent && is_imm_fpr(
|
||||
issue_instr_i[i].op
|
||||
)) ? rd_clobber_fpr[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE : 0);
|
||||
|
||||
assign rs3_valid[i] = rs3_available[i];
|
||||
assign rs3_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(issue_instr_i[i].op));
|
||||
|
||||
end
|
||||
|
||||
// ---------------
|
||||
|
|
@ -902,40 +786,6 @@ module issue_read_operands
|
|||
end
|
||||
end
|
||||
|
||||
always_comb begin : gen_check_waw_dependencies
|
||||
stall_waw = '1;
|
||||
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
|
||||
if (issue_instr_valid_i[i] && !fu_busy[i]) begin
|
||||
// -----------------------------------------
|
||||
// WAW - Write After Write Dependency Check
|
||||
// -----------------------------------------
|
||||
// no other instruction has the same destination register -> issue the instruction
|
||||
if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
issue_instr_i[i].op
|
||||
)) ? (rd_clobber_fpr[issue_instr_i[i].rd] == NONE) :
|
||||
(rd_clobber_gpr[issue_instr_i[i].rd] == NONE)) begin
|
||||
stall_waw[i] = 1'b0;
|
||||
end
|
||||
// or check that the target destination register will be written in this cycle by the
|
||||
// commit stage
|
||||
for (int unsigned c = 0; c < CVA6Cfg.NrCommitPorts; c++) begin
|
||||
if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
issue_instr_i[i].op
|
||||
)) ? (we_fpr_i[c] && waddr_i[c] == issue_instr_i[i].rd) :
|
||||
(we_gpr_i[c] && waddr_i[c] == issue_instr_i[i].rd)) begin
|
||||
stall_waw[i] = 1'b0;
|
||||
end
|
||||
end
|
||||
if (i > 0) begin
|
||||
if ((issue_instr_i[i].rd == issue_instr_i[i-1].rd) && (issue_instr_i[i].rd != '0)) begin
|
||||
stall_waw[i] = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// We can issue an instruction if we do not detect that any other instruction is writing the same
|
||||
// destination register.
|
||||
// We also need to check if there is an unresolved branch in the scoreboard.
|
||||
|
|
@ -946,7 +796,7 @@ module issue_read_operands
|
|||
// check that the instruction we got is valid
|
||||
// and that the functional unit we need is not busy
|
||||
if (issue_instr_valid_i[i] && !fu_busy[i]) begin
|
||||
if (!stall_raw[i] && !stall_waw[i]) begin
|
||||
if (!stall_raw[i]) begin
|
||||
issue_ack[i] = 1'b1;
|
||||
end
|
||||
if (issue_instr_i[i].ex.valid) begin
|
||||
|
|
|
|||
121
core/raw_checker.sv
Normal file
121
core/raw_checker.sv
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
// Copyright 2024 Thales DIS France SAS
|
||||
//
|
||||
// Licensed under the Solderpad Hardware Licence, Version 0.51 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
// You may obtain a copy of the License at https://solderpad.org/licenses/
|
||||
//
|
||||
// Original Author: Junheng Zheng - Thales
|
||||
|
||||
module raw_checker
|
||||
import ariane_pkg::*;
|
||||
#(
|
||||
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
|
||||
) (
|
||||
// Subsystem Clock - SUBSYSTEM
|
||||
input logic clk_i,
|
||||
// Asynchronous reset active low - SUBSYSTEM
|
||||
input logic rst_ni,
|
||||
// Register source of the instruction to check RAW dependancies - SCOREBOARD
|
||||
input logic [REG_ADDR_SIZE-1:0] rs_i,
|
||||
// Type of register source (FPR or GPR) - SCOREBOARD
|
||||
input logic rs_fpr_i,
|
||||
// Registers of destination of the instructions already issued in the scoreboard - SCOREBOARD
|
||||
input logic [CVA6Cfg.NR_SB_ENTRIES-1:0][REG_ADDR_SIZE-1:0] rd_i,
|
||||
// Type of registers of destination (FPR or GPR) - SCOREBOARD
|
||||
input logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rd_fpr_i,
|
||||
// Instructions in the scoreboard are still issued - SCOREBOARD
|
||||
input logic [CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued_i,
|
||||
// Issue pointer - SCOREBOARD
|
||||
input logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i,
|
||||
|
||||
// Index in the scoreboard of the most recent RAW dependancy - SCOREBOARD
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] idx_o,
|
||||
// Indicates if there is a RAW dependancy - SCOREBOARD
|
||||
output logic valid_o
|
||||
);
|
||||
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES-1:0] same_rd_as_rs;
|
||||
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES-1:0] same_rd_as_rs_before;
|
||||
logic last_before_valid;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] last_before_idx;
|
||||
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES-1:0] same_rd_as_rs_after;
|
||||
logic last_after_valid;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] last_after_idx;
|
||||
|
||||
logic valid;
|
||||
logic rs_is_gpr0;
|
||||
|
||||
for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
|
||||
assign same_rd_as_rs[i] = (rs_fpr_i == rd_fpr_i[i]) && (rs_i == rd_i[i]) && still_issued_i[i];
|
||||
assign same_rd_as_rs_before[i] = (i < issue_pointer_i) && same_rd_as_rs[i];
|
||||
assign same_rd_as_rs_after[i] = (i >= issue_pointer_i) && same_rd_as_rs[i];
|
||||
end
|
||||
|
||||
//Last finders
|
||||
// for instructions < instruction pointer
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES),
|
||||
.DataWidth(1),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_last_finder_before (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.flush_i(1'b0),
|
||||
.rr_i ({$clog2(CVA6Cfg.NR_SB_ENTRIES){1'b1}}), // Highest index has highest prio.
|
||||
.req_i (same_rd_as_rs_before),
|
||||
.gnt_o (),
|
||||
.data_i ('0),
|
||||
.gnt_i (1'b1),
|
||||
.req_o (last_before_valid),
|
||||
.data_o (),
|
||||
.idx_o (last_before_idx)
|
||||
);
|
||||
|
||||
// for instructions >= instruction pointer
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES),
|
||||
.DataWidth(1),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_last_finder_after (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.flush_i(1'b0),
|
||||
.rr_i ({$clog2(CVA6Cfg.NR_SB_ENTRIES){1'b1}}), // Highest index has highest prio.
|
||||
.req_i (same_rd_as_rs_after),
|
||||
.gnt_o (),
|
||||
.data_i ('0),
|
||||
.gnt_i (1'b1),
|
||||
.req_o (last_after_valid),
|
||||
.data_o (),
|
||||
.idx_o (last_after_idx)
|
||||
);
|
||||
|
||||
// take the minimum of the last indexes
|
||||
rr_arb_tree #(
|
||||
.NumIn(2),
|
||||
.DataWidth(CVA6Cfg.TRANS_ID_BITS),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) min_finder (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.flush_i(1'b0),
|
||||
.rr_i ('0), // Lowest index has highest prio.
|
||||
.req_i ({last_after_valid,last_before_valid}),
|
||||
.gnt_o (),
|
||||
.data_i ({last_after_idx,last_before_idx}),
|
||||
.gnt_i (1'b1),
|
||||
.req_o (valid),
|
||||
.data_o (idx_o),
|
||||
.idx_o ()
|
||||
);
|
||||
|
||||
assign rs_is_gpr0 = (rs_i == '0) && !rs_fpr_i;
|
||||
assign valid_o = valid && !rs_is_gpr0;
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue