mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-06-27 17:00:57 -04:00
c784fd9047
This PR introduces a new RAW hazard detection mechanism to eliminate WAW hazards in CVA6 issue stage. It first checks for hazards in all scoreboard entries in parallel. Then it filters found hazards before vs after the current issue pointer. It then finds the index of the last hazard before (resp. after) the issue pointer. Finally, it gives precedence to a hazard before the issue pointer over the one after the issue pointer. --------- Co-authored-by: Junheng Zheng <junheng.zheng@thalesgroup.com> Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
202 lines
9 KiB
Text
202 lines
9 KiB
Text
//////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2021 OpenHW Group
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Manifest for the CVA6 CORE RTL model.
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// - This is a CORE-ONLY manifest.
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// - Relevent synthesis and simulation scripts/Makefiles must set the shell
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// ENV variable CVA6_REPO_DIR.
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//
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///////////////////////////////////////////////////////////////////////////////
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//FPGA memories
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv
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+incdir+${CVA6_REPO_DIR}/core/include/
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+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
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+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
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+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/axi/include/
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+incdir+${CVA6_REPO_DIR}/common/local/util/
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// Floating point unit
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_pkg.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_cast_multi.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_classifier.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_divsqrt_multi.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_fma_multi.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_fma.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_noncomp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_opgroup_block.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_rounding.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_top.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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${CVA6_REPO_DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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${CVA6_REPO_DIR}/core/include/config_pkg.sv
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${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
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${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
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// Note: depends on fpnew_pkg, above
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${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
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// Packages
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${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
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${CVA6_REPO_DIR}/core/include/build_config_pkg.sv
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//CVXIF
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${CVA6_REPO_DIR}/core/cvxif_compressed_if_driver.sv
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${CVA6_REPO_DIR}/core/cvxif_issue_register_commit_if_driver.sv
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${CVA6_REPO_DIR}/core/cvxif_example/include/cvxif_instr_pkg.sv
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${CVA6_REPO_DIR}/core/cvxif_fu.sv
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${CVA6_REPO_DIR}/core/cvxif_example/cvxif_example_coprocessor.sv
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${CVA6_REPO_DIR}/core/cvxif_example/instr_decoder.sv
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${CVA6_REPO_DIR}/core/cvxif_example/compressed_instr_decoder.sv
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${CVA6_REPO_DIR}/core/cvxif_example/copro_alu.sv
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// Common Cells
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_arbiter.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_mux.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_demux.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
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// Common Cells for example coprocessor
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/counter.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/delta_counter.sv
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// Top-level source files (not necessarily instantiated at the top of the cva6).
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${CVA6_REPO_DIR}/core/cva6.sv
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${CVA6_REPO_DIR}/core/cva6_rvfi_probes.sv
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${CVA6_REPO_DIR}/core/alu.sv
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// Note: depends on fpnew_pkg, above
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${CVA6_REPO_DIR}/core/fpu_wrap.sv
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${CVA6_REPO_DIR}/core/branch_unit.sv
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${CVA6_REPO_DIR}/core/compressed_decoder.sv
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${CVA6_REPO_DIR}/core/macro_decoder.sv
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${CVA6_REPO_DIR}/core/controller.sv
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${CVA6_REPO_DIR}/core/zcmt_decoder.sv
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${CVA6_REPO_DIR}/core/csr_buffer.sv
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${CVA6_REPO_DIR}/core/csr_regfile.sv
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${CVA6_REPO_DIR}/core/decoder.sv
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${CVA6_REPO_DIR}/core/ex_stage.sv
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${CVA6_REPO_DIR}/core/instr_realign.sv
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${CVA6_REPO_DIR}/core/id_stage.sv
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${CVA6_REPO_DIR}/core/issue_read_operands.sv
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${CVA6_REPO_DIR}/core/issue_stage.sv
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${CVA6_REPO_DIR}/core/load_unit.sv
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${CVA6_REPO_DIR}/core/load_store_unit.sv
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${CVA6_REPO_DIR}/core/lsu_bypass.sv
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${CVA6_REPO_DIR}/core/mult.sv
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${CVA6_REPO_DIR}/core/multiplier.sv
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${CVA6_REPO_DIR}/core/serdiv.sv
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${CVA6_REPO_DIR}/core/perf_counters.sv
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${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
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${CVA6_REPO_DIR}/core/ariane_regfile_fpga.sv
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// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
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${CVA6_REPO_DIR}/core/scoreboard.sv
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${CVA6_REPO_DIR}/core/raw_checker.sv
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${CVA6_REPO_DIR}/core/store_buffer.sv
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${CVA6_REPO_DIR}/core/amo_buffer.sv
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${CVA6_REPO_DIR}/core/store_unit.sv
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${CVA6_REPO_DIR}/core/commit_stage.sv
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${CVA6_REPO_DIR}/core/axi_shim.sv
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${CVA6_REPO_DIR}/core/cva6_accel_first_pass_decoder_stub.sv
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${CVA6_REPO_DIR}/core/acc_dispatcher.sv
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${CVA6_REPO_DIR}/core/cva6_fifo_v3.sv
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// What is "frontend"?
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${CVA6_REPO_DIR}/core/frontend/btb.sv
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${CVA6_REPO_DIR}/core/frontend/bht.sv
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${CVA6_REPO_DIR}/core/frontend/bht2lvl.sv
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${CVA6_REPO_DIR}/core/frontend/ras.sv
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${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
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${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
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${CVA6_REPO_DIR}/core/frontend/frontend.sv
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// Cache subsystem
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/tag_cmp.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/axi_adapter.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/miss_handler.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cache_ctrl.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache_axi_wrapper.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/std_cache_subsystem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/std_nbdcache.sv
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-F ${HPDCACHE_DIR}/rtl/hpdcache.Flist
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${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_resp_demux.sv
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${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_read.sv
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${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_write.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_if_adapter.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_wrapper.sv
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${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv
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${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv
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${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv
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// Physical Memory Protection
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// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
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${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
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${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
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${CVA6_REPO_DIR}/core/pmp/src/pmp_data_if.sv
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// Tracer (behavioral code, not RTL)
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${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
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${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
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${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper_cache_techno.sv
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${CVA6_REPO_DIR}/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
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${CVA6_REPO_DIR}/common/local/util/sram.sv
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${CVA6_REPO_DIR}/common/local/util/sram_cache.sv
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// MMU
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${CVA6_REPO_DIR}/core/cva6_mmu/cva6_mmu.sv
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${CVA6_REPO_DIR}/core/cva6_mmu/cva6_ptw.sv
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${CVA6_REPO_DIR}/core/cva6_mmu/cva6_tlb.sv
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${CVA6_REPO_DIR}/core/cva6_mmu/cva6_shared_tlb.sv
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// end of manifest
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