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Added decoding of LD/ST instructions
This commit is contained in:
Florian Zaruba
parent
ff54341edb
commit
cbdf579903
7 changed files with 60 additions and 8 deletions
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@ -71,7 +71,7 @@ module ariane
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logic [31:0] instr_rdata_id_o;
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logic is_compressed_id_o;
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logic illegal_c_insn_id_o;
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logic [63:0] pc_if_o;
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logic [63:0] pc_if_o, imm_o;
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logic [63:0] pc_id_o;
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logic comparison_result_o;
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logic lsu_ready_o;
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@ -151,6 +151,7 @@ module ariane
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.operator_o ( operator_o ),
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.operand_a_o ( operand_a_o ),
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.operand_b_o ( operand_b_o ),
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.imm_o ( imm_o ),
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.trans_id_o ( trans_id_o ),
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.alu_ready_i ( alu_ready_i ),
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.alu_valid_o ( alu_valid_i ),
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@ -176,6 +177,7 @@ module ariane
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.operator_i ( operator_o ),
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.operand_a_i ( operand_a_o ),
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.operand_b_i ( operand_b_o ),
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.imm_i ( imm_o ),
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.trans_id_i ( trans_id_o ),
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.comparison_result_o ( comparison_result_o ),
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41
decoder.sv
41
decoder.sv
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@ -175,13 +175,50 @@ module decoder (
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end
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OPCODE_STORE: begin
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// TODO: Implement
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instruction_o.fu = LSU;
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imm_select = SIMM;
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instruction_o.rs1 = instr.stype.rs1;
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instruction_o.rs2 = instr.stype.rs2;
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// determine store size
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unique case (instr.stype.funct3)
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3'b000:
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instruction_o.op = SB;
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3'b001:
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instruction_o.op = SH;
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3'b010:
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instruction_o.op = SW;
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3'b011:
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instruction_o.op = SD;
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default:
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illegal_instr_o = 1'b1;
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endcase
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end
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OPCODE_LOAD: begin
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// TODO: Implement
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instruction_o.fu = LSU;
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imm_select = IIMM;
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instruction_o.rs1 = instr.itype.rs1;
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instruction_o.rd = instr.itype.rd;
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// determine load size and signed type
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unique case (instr.itype.funct3)
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3'b000:
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instruction_o.op = LB;
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3'b001:
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instruction_o.op = LH;
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3'b010:
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instruction_o.op = LW;
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3'b100:
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instruction_o.op = LBU;
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3'b101:
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instruction_o.op = LHU;
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3'b110:
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instruction_o.op = LW;
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3'b011:
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instruction_o.op = LD;
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default:
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illegal_instr_o = 1'b1;
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endcase
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end
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OPCODE_BRANCH: begin
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@ -25,6 +25,7 @@ module ex_stage (
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input fu_op operator_i,
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input logic [63:0] operand_a_i,
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input logic [63:0] operand_b_i,
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input logic [63:0] imm_i,
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input logic [TRANS_ID_BITS-1:0] trans_id_i,
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// ALU 1
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@ -28,6 +28,7 @@ module id_stage #(
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output fu_op operator_o,
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output logic [63:0] operand_a_o,
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output logic [63:0] operand_b_o,
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output logic [63:0] imm_o,
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output logic [TRANS_ID_BITS-1:0] trans_id_o,
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input logic alu_ready_i,
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@ -128,6 +129,7 @@ module id_stage #(
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.operator_o (operator_o ),
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.operand_a_o (operand_a_o ),
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.operand_b_o (operand_b_o ),
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.imm_o (imm_o ),
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.trans_id_o (trans_id_o ),
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.alu_ready_i (alu_ready_i ),
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.alu_valid_o (alu_valid_o ),
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@ -50,7 +50,7 @@ package ariane_pkg;
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LTS, LTU, LES, LEU, GTS, GTU, GES, GEU, EQ, NE, // comparisons
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SLTS, SLTU, SLETS, SLETU, // set lower than operations
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MRET, SRET, URET, ECALL, WRITE, READ, SET, CLEAR, // CSR functions
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LD, SD, LW, SW, LH, SH, LB, SB, LBU, SBU // LSU functions
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LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU, SBU // LSU functions
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} fu_op;
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// ---------------
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@ -33,6 +33,7 @@ module issue_read_operands (
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output fu_op operator_o,
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output logic [63:0] operand_a_o,
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output logic [63:0] operand_b_o,
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output logic [63:0] imm_o, // output immediate for the LSU
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output logic [TRANS_ID_BITS-1:0] trans_id_o,
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// ALU 1
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input logic alu_ready_i, // FU is ready
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@ -55,7 +56,7 @@ module issue_read_operands (
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logic [63:0] operand_a_regfile, operand_b_regfile; // operands coming from regfile
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// output flipflop (ID <-> EX)
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logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q;
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logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q, imm_n, imm_q;
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logic alu_valid_n, alu_valid_q;
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logic [TRANS_ID_BITS-1:0] trans_id_n, trans_id_q;
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fu_op operator_n, operator_q;
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@ -68,6 +69,7 @@ module issue_read_operands (
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assign operator_o = operator_q;
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assign alu_valid_o = alu_valid_q;
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assign trans_id_o = trans_id_q;
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assign imm_o = imm_q;
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// ---------------
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// Issue Stage
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// ---------------
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@ -160,11 +162,16 @@ module issue_read_operands (
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operand_a_n = issue_instr_i.ex.epc;
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end
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// or is it an immediate (including PC)
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if (issue_instr_i.use_imm) begin
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// or is it an immediate (including PC), this is not the case for a store
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if (issue_instr_i.use_imm && issue_instr_i.op != SD
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&& issue_instr_i.op != SW
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&& issue_instr_i.op != SH
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&& issue_instr_i.op != SB
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&& issue_instr_i.op != SBU ) begin
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operand_b_n = issue_instr_i.result;
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end
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// immediates are the third operands in the store case
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imm_n = issue_instr_i.result;
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trans_id_n = issue_instr_i.trans_id;
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operator_n = issue_instr_i.op;
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end
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3
lsu.sv
3
lsu.sv
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@ -47,4 +47,7 @@ module lsu (
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);
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// exception unit
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// misaligned detector
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endmodule
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