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pmp: Wire pmp registers to lsu

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This commit is contained in:
Moritz Schneider 2019-10-03 16:33:38 +02:00 • committed by Florian Zaruba
parent 9cbc7da177
commit d210a1430b
6 changed files with 62 additions and 48 deletions
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2
Makefile
View file

@ -81,6 +81,7 @@ ariane_pkg := include/riscv_pkg.sv \
include/axi_intf.sv \
tb/ariane_soc_pkg.sv \
include/ariane_axi_pkg.sv \
src/pmp/include/pmp_pkg.sv \
src/fpu/src/fpnew_pkg.sv \
src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
@ -138,6 +139,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(wildcard src/axi_node/src/*.sv) \
$(wildcard src/axi_riscv_atomics/src/*.sv) \
$(wildcard src/axi_mem_if/src/*.sv) \
$(wildcard src/pmp/src/*.sv) \
src/rv_plic/rtl/rv_plic_target.sv \
src/rv_plic/rtl/rv_plic_gateway.sv \
src/rv_plic/rtl/plic_regmap.sv \

5
src/ariane.sv
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@ -428,7 +428,10 @@ module ariane #(
// DCACHE interfaces
.dcache_req_ports_i ( dcache_req_ports_cache_ex ),
.dcache_req_ports_o ( dcache_req_ports_ex_cache ),
.dcache_wbuffer_empty_i ( dcache_commit_wbuffer_empty )
.dcache_wbuffer_empty_i ( dcache_commit_wbuffer_empty ),
// PMP
.pmpcfg_i ( pmpcfg ),
.pmpaddr_i ( pmpaddr )
);
// ---------

9
src/ex_stage.sv
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@ -99,7 +99,10 @@ module ex_stage #(
input amo_resp_t amo_resp_i, // response from cache subsystem
// Performance counters
output logic itlb_miss_o,
output logic dtlb_miss_o
output logic dtlb_miss_o,
// PMPs
input riscv::pmpcfg_t [15:0] pmpcfg_i,
input logic[ArianeCfg.NrPMPEntries-1:0] pmpaddr_i
);
// -------------------------
@ -297,7 +300,9 @@ module ex_stage #(
.dcache_wbuffer_empty_i,
.amo_valid_commit_i,
.amo_req_o,
.amo_resp_i
.amo_resp_i,
.pmpcfg_i,
.pmpaddr_i
);
endmodule

5
src/load_store_unit.sv
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@ -66,7 +66,10 @@ module load_store_unit #(
input logic dcache_wbuffer_empty_i,
// AMO interface
output amo_req_t amo_req_o,
input amo_resp_t amo_resp_i
input amo_resp_t amo_resp_i,
// PMP
input riscv::pmpcfg_t [15:0] pmpcfg_i,
input logic[ArianeCfg.NrPMPEntries-1:0] pmpaddr_i
);
// data is misaligned
logic data_misaligned;

88
src/mmu.sv
View file

@ -17,48 +17,48 @@
import ariane_pkg::*;
module mmu #(
parameter int unsigned INSTR_TLB_ENTRIES = 4,
parameter int unsigned DATA_TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
parameter int unsigned INSTR_TLB_ENTRIES = 4,
parameter int unsigned DATA_TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
input logic clk_i,
input logic rst_ni,
input logic flush_i,
input logic enable_translation_i,
input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
// IF interface
input icache_areq_o_t icache_areq_i,
output icache_areq_i_t icache_areq_o,
// LSU interface
// this is a more minimalistic interface because the actual addressing logic is handled
// in the LSU as we distinguish load and stores, what we do here is simple address translation
input exception_t misaligned_ex_i,
input logic lsu_req_i, // request address translation
input logic [riscv::VLEN-1:0] lsu_vaddr_i, // virtual address in
input logic lsu_is_store_i, // the translation is requested by a store
// if we need to walk the page table we can't grant in the same cycle
// Cycle 0
output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB
// Cycle 1
output logic lsu_valid_o, // translation is valid
output logic [riscv::PLEN-1:0] lsu_paddr_o, // translated address
output exception_t lsu_exception_o, // address translation threw an exception
// General control signals
input riscv::priv_lvl_t priv_lvl_i,
input riscv::priv_lvl_t ld_st_priv_lvl_i,
input logic sum_i,
input logic mxr_i,
// input logic flag_mprv_i,
input logic [43:0] satp_ppn_i,
input logic [ASID_WIDTH-1:0] asid_i,
input logic flush_tlb_i,
// Performance counters
output logic itlb_miss_o,
output logic dtlb_miss_o,
// PTW memory interface
input dcache_req_o_t req_port_i,
output dcache_req_i_t req_port_o
input logic clk_i,
input logic rst_ni,
input logic flush_i,
input logic enable_translation_i,
input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
// IF interface
input icache_areq_o_t icache_areq_i,
output icache_areq_i_t icache_areq_o,
// LSU interface
// this is a more minimalistic interface because the actual addressing logic is handled
// in the LSU as we distinguish load and stores, what we do here is simple address translation
input exception_t misaligned_ex_i,
input logic lsu_req_i, // request address translation
input logic [63:0] lsu_vaddr_i, // virtual address in
input logic lsu_is_store_i, // the translation is requested by a store
// if we need to walk the page table we can't grant in the same cycle
// Cycle 0
output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB
// Cycle 1
output logic lsu_valid_o, // translation is valid
output logic [63:0] lsu_paddr_o, // translated address
output exception_t lsu_exception_o, // address translation threw an exception
// General control signals
input riscv::priv_lvl_t priv_lvl_i,
input riscv::priv_lvl_t ld_st_priv_lvl_i,
input logic sum_i,
input logic mxr_i,
// input logic flag_mprv_i,
input logic [43:0] satp_ppn_i,
input logic [ASID_WIDTH-1:0] asid_i,
input logic flush_tlb_i,
// Performance counters
output logic itlb_miss_o,
output logic dtlb_miss_o,
// PTW memory interface
input dcache_req_o_t req_port_i,
output dcache_req_i_t req_port_o
);
logic iaccess_err; // insufficient privilege to access this instruction page
@ -151,11 +151,11 @@ module mmu #(
.dtlb_hit_i ( dtlb_lu_hit ),
.dtlb_vaddr_i ( lsu_vaddr_i ),
.req_port_i ( req_port_i ),
.req_port_o ( req_port_o ),
.req_port_i ( req_port_i ),
.req_port_o ( req_port_o ),
.*
);
);
// ila_1 i_ila_1 (
// .clk(clk_i), // input wire clk

1
src/pmp Symbolic link
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@ -0,0 +1 @@
/home/mo/Documents/mixedcriticality/code/iopmp