Implement clear on mis-predict flag

Reduced cycle count by 0.7

include/ariane_pkg.svh

@@ -51,6 +51,7 @@ package ariane_pkg;
         logic        is_lower_16;     // branch instruction is compressed and resides
                                       // in the lower 16 bit of the word
         logic        valid;           // prediction with all its values is valid
+        logic        clear;           // invalidate this entry
     } branchpredict;
 
     // branchpredict scoreboard entry

src/branch_unit.sv

@@ -71,12 +71,13 @@ module branch_unit (
     // here we handle the various possibilities of mis-predicts
     always_comb begin : mispredict_handler
         target_address                   = 64'b0;
-        resolved_branch_o.pc             = 64'b0;
+        resolved_branch_o.pc             = pc_i;
         resolved_branch_o.target_address = 64'b0;
         resolved_branch_o.is_taken       = 1'b0;
         resolved_branch_o.valid          = branch_valid_i;
         resolved_branch_o.is_mispredict  = 1'b0;
         resolved_branch_o.is_lower_16    = 1'b0;
+        resolved_branch_o.clear          = 1'b0;
         resolve_branch_o                 = 1'b0;
         // calculate next PC, depending on whether the instruction is compressed or not this may be different
         next_pc                          = pc_i + ((is_compressed_instr_i) ? 64'h2 : 64'h4);
@@ -128,6 +129,9 @@ module branch_unit (
             // re-set the branch to the next PC
             resolved_branch_o.is_mispredict  = 1'b1;
             resolved_branch_o.target_address = next_pc;
+            // clear this entry so that we are not constantly mis-predicting
+            resolved_branch_o.clear          = 1'b1;
+            resolved_branch_o.valid          = 1'b1;
         end
     end
     // use ALU exception signal for storing instruction fetch exceptions if

src/btb.sv

@@ -87,6 +87,10 @@ module btb #(
             btb_n[update_pc].target_address = branch_predict_i.target_address;
             // as is the information whether this was a compressed branch
             btb_n[update_pc].is_lower_16    = branch_predict_i.is_lower_16;
+            // check if we should invalidate this entry
+            if (branch_predict_i.clear) begin
+                btb_n[update_pc].valid = 1'b0;
+            end
         end
     end
 

tb/core_tb.sv

@@ -129,7 +129,7 @@ module core_tb;
         $readmemh("test/rv64ui-p-add.v", rmem);
 
         // copy bitwise from verilog file
-        for (int i = 0; i < 1024/8; i++) begin
+        for (int i = 0; i < 16384/8; i++) begin
             for (int j = 0; j < 8; j++)
                 core_mem_i.ram_i.mem[i][j] = rmem[i*8 + j];
         end