mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Merge branch 'fpga_dev' of github.com:pulp-platform/ariane into fpga_dev
This commit is contained in:
Florian Zaruba
commit
d7e73be02e
4 changed files with 69 additions and 56 deletions
|
|
@ -88,8 +88,8 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LSB_STUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCK_RATIO">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCK_RATIO">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SPI_MEMORY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SPI_MEM_ADDR_BITS">24</spirit:configurableElementValue>
|
||||
|
|
@ -100,17 +100,17 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI4_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UC_FAMILY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STARTUP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STARTUP_EXT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Async_Clk">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DUAL_QUAD_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">axi_quad_spi_inst</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO1">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
|
||||
|
|
@ -122,8 +122,8 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_HIGHADDR">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_quad_spi_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_INCLUDED">1</spirit:configurableElementValue>
|
||||
|
|
@ -156,6 +156,7 @@
|
|||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FIFO_DEPTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SCK_RATIO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SHARED_STARTUP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE" xilinx:valueSource="user"/>
|
||||
|
|
|
|||
|
|
@ -64,3 +64,8 @@ set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
|
|||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
|
||||
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
|
||||
set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
|
||||
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS33} [get_ports spi_clk_o_2]
|
||||
set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS33} [get_ports spi_ss_2]
|
||||
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33} [get_ports spi_miso_2]
|
||||
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports spi_mosi_2]
|
||||
|
|
|
|||
|
|
@ -14,19 +14,19 @@ module ariane_peripherals #(
|
|||
parameter int AxiDataWidth = -1,
|
||||
parameter bit InclSPI = 0
|
||||
) (
|
||||
input logic clk_i , // Clock
|
||||
input logic rst_ni , // Asynchronous reset active low
|
||||
AXI_BUS.in plic ,
|
||||
AXI_BUS.in uart ,
|
||||
AXI_BUS.in spi ,
|
||||
output logic [1:0] irq_o ,
|
||||
input logic clk_i , // Clock
|
||||
input logic rst_ni , // Asynchronous reset active low
|
||||
AXI_BUS.in plic ,
|
||||
AXI_BUS.in uart ,
|
||||
AXI_BUS.in spi ,
|
||||
output logic [1:0] irq_o ,
|
||||
// UART
|
||||
input logic rx_i ,
|
||||
output logic tx_o ,
|
||||
input logic rx_i ,
|
||||
output logic tx_o ,
|
||||
// SPI
|
||||
output logic spi_clk_o ,
|
||||
output logic spi_mosi ,
|
||||
input logic spi_miso ,
|
||||
output logic spi_clk_o,
|
||||
output logic spi_mosi ,
|
||||
input logic spi_miso ,
|
||||
output logic spi_ss
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -10,44 +10,44 @@
|
|||
|
||||
// Top-level for Genesys 2
|
||||
module ariane_xilinx (
|
||||
input logic cpu_resetn,
|
||||
input logic sys_clk_p,
|
||||
input logic sys_clk_n,
|
||||
inout logic [31:0] ddr3_dq,
|
||||
inout logic [3:0] ddr3_dqs_n,
|
||||
inout logic [3:0] ddr3_dqs_p,
|
||||
output logic [14:0] ddr3_addr,
|
||||
output logic [2:0] ddr3_ba,
|
||||
output logic ddr3_ras_n,
|
||||
output logic ddr3_cas_n,
|
||||
output logic ddr3_we_n,
|
||||
output logic ddr3_reset_n,
|
||||
output logic [0:0] ddr3_ck_p,
|
||||
output logic [0:0] ddr3_ck_n,
|
||||
output logic [0:0] ddr3_cke,
|
||||
output logic [0:0] ddr3_cs_n,
|
||||
output logic [3:0] ddr3_dm,
|
||||
output logic [0:0] ddr3_odt,
|
||||
|
||||
input logic tck,
|
||||
input logic tms,
|
||||
input logic trst_n,
|
||||
input logic tdi,
|
||||
output logic tdo,
|
||||
|
||||
input logic rx,
|
||||
output logic tx,
|
||||
|
||||
output logic [7:0] led,
|
||||
input logic [7:0] sw,
|
||||
output logic fan_pwm,
|
||||
|
||||
// SPI
|
||||
output logic spi_mosi,
|
||||
input logic spi_miso,
|
||||
output logic spi_ss,
|
||||
output logic spi_clk_o
|
||||
//output logic spi_ip2intc_irtp
|
||||
input logic cpu_resetn ,
|
||||
input logic sys_clk_p ,
|
||||
input logic sys_clk_n ,
|
||||
inout logic [31:0] ddr3_dq ,
|
||||
inout logic [ 3:0] ddr3_dqs_n ,
|
||||
inout logic [ 3:0] ddr3_dqs_p ,
|
||||
output logic [14:0] ddr3_addr ,
|
||||
output logic [ 2:0] ddr3_ba ,
|
||||
output logic ddr3_ras_n ,
|
||||
output logic ddr3_cas_n ,
|
||||
output logic ddr3_we_n ,
|
||||
output logic ddr3_reset_n,
|
||||
output logic [ 0:0] ddr3_ck_p ,
|
||||
output logic [ 0:0] ddr3_ck_n ,
|
||||
output logic [ 0:0] ddr3_cke ,
|
||||
output logic [ 0:0] ddr3_cs_n ,
|
||||
output logic [ 3:0] ddr3_dm ,
|
||||
output logic [ 0:0] ddr3_odt ,
|
||||
input logic tck ,
|
||||
input logic tms ,
|
||||
input logic trst_n ,
|
||||
input logic tdi ,
|
||||
output logic tdo ,
|
||||
input logic rx ,
|
||||
output logic tx ,
|
||||
output logic [ 7:0] led ,
|
||||
input logic [ 7:0] sw ,
|
||||
output logic fan_pwm ,
|
||||
// SPI
|
||||
output logic spi_mosi ,
|
||||
input logic spi_miso ,
|
||||
output logic spi_ss ,
|
||||
output logic spi_clk_o ,
|
||||
output logic spi_mosi_2 ,
|
||||
output logic spi_miso_2 ,
|
||||
output logic spi_ss_2 ,
|
||||
output logic spi_clk_o_2
|
||||
//output logic spi_ip2intc_irtp
|
||||
);
|
||||
|
||||
localparam NBSlave = 4; // debug, Instruction fetch, data bypass, data
|
||||
|
|
@ -79,6 +79,12 @@ AXI_BUS #(
|
|||
.AXI_USER_WIDTH ( AxiUserWidth )
|
||||
) master[ariane_soc::NB_PERIPHERALS-1:0]();
|
||||
|
||||
// spi hack
|
||||
assign spi_mosi_2 = spi_mosi;
|
||||
assign spi_miso_2 = spi_miso;
|
||||
assign spi_clk_o_2 = spi_clk_o;
|
||||
assign spi_ss_2 = spi_ss;
|
||||
|
||||
// disable test-enable
|
||||
logic test_en;
|
||||
logic ndmreset;
|
||||
|
|
@ -88,6 +94,7 @@ logic time_irq;
|
|||
logic ipi;
|
||||
|
||||
logic clk;
|
||||
logic spi_clk_i;
|
||||
logic ddr_sync_reset;
|
||||
logic ddr_clock_out;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue