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Add SPI interrupt to PLIC connection
This commit is contained in:
Moritz Schneider
parent
c40eb0be15
commit
dbe63f622e
5 changed files with 88 additions and 79 deletions
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@ -88,7 +88,7 @@
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LSB_STUP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCK_RATIO">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCK_RATIO">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SPI_MEMORY">1</spirit:configurableElementValue>
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@ -100,17 +100,17 @@
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI4_ID_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UC_FAMILY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STARTUP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STARTUP_EXT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Async_Clk">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DUAL_QUAD_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">256</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">axi_quad_spi_inst</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO1">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
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@ -122,8 +122,8 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_HIGHADDR">0x00000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_quad_spi_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_INCLUDED">1</spirit:configurableElementValue>
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@ -156,6 +156,7 @@
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<xilinx:componentInstanceExtensions>
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FIFO_DEPTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SCK_RATIO" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SHARED_STARTUP" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE" xilinx:valueSource="user"/>
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@ -44,3 +44,8 @@ set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
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set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
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set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
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set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
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set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS33} [get_ports spi_clk_o_2]
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set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS33} [get_ports spi_ss_2]
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set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33} [get_ports spi_miso_2]
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set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports spi_mosi_2]
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@ -13,21 +13,20 @@ module ariane_peripherals #(
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parameter AxiAddrWidth = -1,
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parameter AxiDataWidth = -1
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) (
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input logic clk_i , // Clock
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input logic rst_ni , // Asynchronous reset active low
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AXI_BUS.in plic ,
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AXI_BUS.in uart ,
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AXI_BUS.in spi ,
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output logic [1:0] irq_o ,
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input logic clk_i , // Clock
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input logic rst_ni , // Asynchronous reset active low
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AXI_BUS.in plic ,
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AXI_BUS.in uart ,
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AXI_BUS.in spi ,
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output logic [1:0] irq_o ,
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// UART
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input logic rx_i ,
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output logic tx_o ,
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input logic rx_i ,
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output logic tx_o ,
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// SPI
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output logic spi_clk_o ,
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output logic spi_mosi ,
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input logic spi_miso ,
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output logic spi_ss ,
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output logic spi_ip2intc_irtp
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output logic spi_clk_o,
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output logic spi_mosi ,
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input logic spi_miso ,
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output logic spi_ss
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);
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// ---------------
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@ -469,12 +468,10 @@ module ariane_peripherals #(
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.ss_i ('0 ),
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.ss_o (spi_ss ),
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.ss_t ('0 ),
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.ip2intc_irpt (spi_ip2intc_irtp ),
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.cfgclk (spi_clk_o ), // output wire cfgclk
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.cfgmclk ( ), // output wire cfgmclk
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.eos ( ), // output wire eos
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.preq ( ) // output wire preq
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.ip2intc_irpt (irq_sources[1] ),
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.sck_i ('0 ),
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.sck_o (spi_clk_o ),
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.sck_t ('0 )
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);
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@ -10,44 +10,44 @@
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// Top-level for Genesys 2
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module ariane_xilinx (
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input logic cpu_resetn,
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input logic sys_clk_p,
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input logic sys_clk_n,
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inout logic [31:0] ddr3_dq,
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inout logic [3:0] ddr3_dqs_n,
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inout logic [3:0] ddr3_dqs_p,
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output logic [14:0] ddr3_addr,
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output logic [2:0] ddr3_ba,
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output logic ddr3_ras_n,
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output logic ddr3_cas_n,
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output logic ddr3_we_n,
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output logic ddr3_reset_n,
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output logic [0:0] ddr3_ck_p,
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output logic [0:0] ddr3_ck_n,
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output logic [0:0] ddr3_cke,
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output logic [0:0] ddr3_cs_n,
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output logic [3:0] ddr3_dm,
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output logic [0:0] ddr3_odt,
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input logic tck,
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input logic tms,
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input logic trst_n,
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input logic tdi,
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output logic tdo,
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input logic rx,
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output logic tx,
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output logic [7:0] led,
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input logic [7:0] sw,
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output logic fan_pwm,
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// SPI
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output logic spi_mosi,
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input logic spi_miso,
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output logic spi_ss,
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output logic spi_clk_o
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//output logic spi_ip2intc_irtp
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input logic cpu_resetn ,
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input logic sys_clk_p ,
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input logic sys_clk_n ,
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inout logic [31:0] ddr3_dq ,
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inout logic [ 3:0] ddr3_dqs_n ,
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inout logic [ 3:0] ddr3_dqs_p ,
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output logic [14:0] ddr3_addr ,
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output logic [ 2:0] ddr3_ba ,
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output logic ddr3_ras_n ,
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output logic ddr3_cas_n ,
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output logic ddr3_we_n ,
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output logic ddr3_reset_n,
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output logic [ 0:0] ddr3_ck_p ,
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output logic [ 0:0] ddr3_ck_n ,
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output logic [ 0:0] ddr3_cke ,
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output logic [ 0:0] ddr3_cs_n ,
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output logic [ 3:0] ddr3_dm ,
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output logic [ 0:0] ddr3_odt ,
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input logic tck ,
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input logic tms ,
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input logic trst_n ,
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input logic tdi ,
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output logic tdo ,
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input logic rx ,
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output logic tx ,
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output logic [ 7:0] led ,
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input logic [ 7:0] sw ,
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output logic fan_pwm ,
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// SPI
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output logic spi_mosi ,
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input logic spi_miso ,
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output logic spi_ss ,
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output logic spi_clk_o ,
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output logic spi_mosi_2 ,
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output logic spi_miso_2 ,
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output logic spi_ss_2 ,
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output logic spi_clk_o_2
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//output logic spi_ip2intc_irtp
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);
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localparam NBSlave = 4; // debug, Instruction fetch, data bypass, data
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@ -79,6 +79,12 @@ AXI_BUS #(
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.AXI_USER_WIDTH ( AxiUserWidth )
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) master[ariane_soc::NB_PERIPHERALS-1:0]();
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// spi hack
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assign spi_mosi_2 = spi_mosi;
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assign spi_miso_2 = spi_miso;
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assign spi_clk_o_2 = spi_clk_o;
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assign spi_ss_2 = spi_ss;
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// disable test-enable
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logic test_en;
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logic ndmreset;
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@ -88,6 +94,7 @@ logic time_irq;
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logic ipi;
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logic clk;
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logic spi_clk_i;
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logic ddr_sync_reset;
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logic ddr_clock_out;
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@ -413,22 +420,21 @@ bootrom i_bootrom (
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// Peripherals
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// ---------------
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ariane_peripherals #(
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.AxiAddrWidth(AxiAddrWidth),
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.AxiDataWidth(AxiDataWidth)
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.AxiAddrWidth(AxiAddrWidth),
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.AxiDataWidth(AxiDataWidth)
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) i_ariane_peripherals (
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.clk_i (clk ),
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.rst_ni (ndmreset_n ),
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.plic (master[ariane_soc::PLIC]),
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.uart (master[ariane_soc::UART]),
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.spi (master[ariane_soc::SPI] ),
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.irq_o (irq ),
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.rx_i (rx ),
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.tx_o (tx ),
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.spi_clk_o (spi_clk_o ),
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.spi_mosi (spi_mosi ),
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.spi_miso (spi_miso ),
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.spi_ss (spi_ss ),
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.spi_ip2intc_irtp( )
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.clk_i (clk ),
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.rst_ni (ndmreset_n ),
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.plic (master[ariane_soc::PLIC]),
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.uart (master[ariane_soc::UART]),
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.spi (master[ariane_soc::SPI] ),
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.irq_o (irq ),
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.rx_i (rx ),
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.tx_o (tx ),
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.spi_clk_o(spi_clk_o ),
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.spi_mosi (spi_mosi ),
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.spi_miso (spi_miso ),
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.spi_ss (spi_ss )
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);
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// ---------------------
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@ -14,7 +14,7 @@ package ariane_soc;
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localparam NB_PERIPHERALS = 7;
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localparam NumTargets = 2;
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localparam NumSources = 1;
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localparam NumSources = 2;
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typedef enum int unsigned {
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DRAM = 0,
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