mirror of
https://github.com/openhwgroup/cva6.git
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Verible fix
This commit is contained in:
Maxime COLSON
parent
99596541fd
commit
d83789fa4f
6 changed files with 129 additions and 127 deletions
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@ -9,26 +9,25 @@
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//Systollic module used to determines the iaddr, ilastsize, iretire for Encoder Module
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module instr_to_trace
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#(
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module instr_to_trace #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter type uop_entry_t = logic,
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parameter type itt_out_t = logic,
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parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC
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parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4)
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parameter IRETIRE_LEN = 32 //Size is iretire_width_p in the E-Trace SPEC
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)(
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input uop_entry_t uop_entry_i,
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input logic [CAUSE_LEN-1:0] cause_i,
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input logic [CVA6Cfg.XLEN-1:0] tval_i,
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input logic [IRETIRE_LEN-1:0] counter_i,
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input logic [CVA6Cfg.XLEN-1:0] iaddr_i,
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input logic was_special_i,
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parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC
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parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4)
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parameter IRETIRE_LEN = 32 //Size is iretire_width_p in the E-Trace SPEC
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) (
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input uop_entry_t uop_entry_i,
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input logic [ CAUSE_LEN-1:0] cause_i,
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input logic [CVA6Cfg.XLEN-1:0] tval_i,
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input logic [ IRETIRE_LEN-1:0] counter_i,
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input logic [CVA6Cfg.XLEN-1:0] iaddr_i,
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input logic was_special_i,
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output itt_out_t itt_out_o,
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output logic [IRETIRE_LEN-1:0] counter_o,
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output logic [CVA6Cfg.XLEN-1:0] iaddr_o,
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output logic is_special_o
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output itt_out_t itt_out_o,
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output logic [ IRETIRE_LEN-1:0] counter_o,
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output logic [CVA6Cfg.XLEN-1:0] iaddr_o,
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output logic is_special_o
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);
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logic special_inst;
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@ -45,52 +44,52 @@ module instr_to_trace
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itt_out_o = '0;
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if (uop_entry_i.valid) begin
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counter_o = uop_entry_i.compressed ? counter_i + 1 : counter_i + 2;
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counter_o = uop_entry_i.compressed ? counter_i + 1 : counter_i + 2;
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if (was_special_i) begin
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counter_o = 0;
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iaddr_o = uop_entry_i.pc;
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is_special_o = 1'b0;
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end
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if (was_special_i) begin
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counter_o = 0;
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iaddr_o = uop_entry_i.pc;
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is_special_o = 1'b0;
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end
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if (special_inst) begin
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itt_out_o.valid = 1'b1;
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itt_out_o.iretire = uop_entry_i.compressed ? counter_o + 1 : counter_o + 2;
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itt_out_o.itype = uop_entry_i.itype;
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itt_out_o.ilastsize = ~uop_entry_i.compressed;
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itt_out_o.iaddr = iaddr_o;
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itt_out_o.priv = uop_entry_i.priv;
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itt_out_o.cycles = uop_entry_i.cycles;
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itt_out_o.cause = '0;
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itt_out_o.tval = '0;
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is_special_o = 1'b1;
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end
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if (special_inst) begin
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itt_out_o.valid = 1'b1;
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itt_out_o.iretire = uop_entry_i.compressed ? counter_o + 1 : counter_o + 2;
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itt_out_o.itype = uop_entry_i.itype;
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itt_out_o.ilastsize = ~uop_entry_i.compressed;
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itt_out_o.iaddr = iaddr_o;
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itt_out_o.priv = uop_entry_i.priv;
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itt_out_o.cycles = uop_entry_i.cycles;
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itt_out_o.cause = '0;
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itt_out_o.tval = '0;
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is_special_o = 1'b1;
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end
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if (interrupt) begin
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itt_out_o.valid = 1'b1;
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itt_out_o.iretire = uop_entry_i.compressed ? 1 : 2;
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itt_out_o.itype = uop_entry_i.itype;
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itt_out_o.ilastsize = ~uop_entry_i.compressed;
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itt_out_o.iaddr = uop_entry_i.pc;
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itt_out_o.priv = uop_entry_i.priv;
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itt_out_o.cycles = uop_entry_i.cycles;
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itt_out_o.cause = cause_i;
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itt_out_o.tval = '0;
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is_special_o = 1'b1;
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end
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if (interrupt) begin
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itt_out_o.valid = 1'b1;
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itt_out_o.iretire = uop_entry_i.compressed ? 1 : 2;
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itt_out_o.itype = uop_entry_i.itype;
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itt_out_o.ilastsize = ~uop_entry_i.compressed;
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itt_out_o.iaddr = uop_entry_i.pc;
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itt_out_o.priv = uop_entry_i.priv;
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itt_out_o.cycles = uop_entry_i.cycles;
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itt_out_o.cause = cause_i;
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itt_out_o.tval = '0;
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is_special_o = 1'b1;
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end
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if(exception) begin
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itt_out_o.valid = 1'b1;
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itt_out_o.iretire = uop_entry_i.compressed ? 1 : 2;
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itt_out_o.itype = uop_entry_i.itype;
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itt_out_o.ilastsize = ~uop_entry_i.compressed;
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itt_out_o.iaddr = uop_entry_i.pc;
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itt_out_o.priv = uop_entry_i.priv;
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itt_out_o.cycles = uop_entry_i.cycles;
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itt_out_o.cause = cause_i;
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itt_out_o.tval = tval_i;
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is_special_o = 1'b1;
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end
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if (exception) begin
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itt_out_o.valid = 1'b1;
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itt_out_o.iretire = uop_entry_i.compressed ? 1 : 2;
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itt_out_o.itype = uop_entry_i.itype;
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itt_out_o.ilastsize = ~uop_entry_i.compressed;
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itt_out_o.iaddr = uop_entry_i.pc;
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itt_out_o.priv = uop_entry_i.priv;
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itt_out_o.cycles = uop_entry_i.cycles;
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itt_out_o.cause = cause_i;
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itt_out_o.tval = tval_i;
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is_special_o = 1'b1;
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end
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end
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end
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endmodule
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endmodule
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@ -11,9 +11,9 @@
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module cva6_iti #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC
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parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4)
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parameter IRETIRE_LEN = 32, //Size is iretire_width_p in the E-Trace SPEC
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parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC
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parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4)
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parameter IRETIRE_LEN = 32, //Size is iretire_width_p in the E-Trace SPEC
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parameter type rvfi_to_iti_t = logic,
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parameter type iti_to_encoder_t = logic
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) (
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@ -30,7 +30,7 @@ module cva6_iti #(
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// pragma translate_off
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int f;
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initial begin
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f = $fopen("iti.trace","w");
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f = $fopen("iti.trace", "w");
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end
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final $fclose(f);
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// pragma translate_on
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@ -53,8 +53,8 @@ module cva6_iti #(
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logic ilastsize;
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logic [CVA6Cfg.XLEN-1:0] iaddr;
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riscv::priv_lvl_t priv;
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logic [CAUSE_LEN-1:0] cause;
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logic [CVA6Cfg.XLEN-1:0] tval;
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logic [CAUSE_LEN-1:0] cause;
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logic [CVA6Cfg.XLEN-1:0] tval;
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logic [63:0] cycles;
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};
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@ -71,8 +71,8 @@ module cva6_iti #(
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logic [CVA6Cfg.NrCommitPorts-1:0][IRETIRE_LEN-1:0] counter_itt;
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logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] addr_itt;
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logic [CVA6Cfg.NrCommitPorts-1:0] special_itt;
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logic [CVA6Cfg.NrCommitPorts-1:0][CAUSE_LEN-1:0] cause_itt ;
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logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] tval_itt ;
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logic [CVA6Cfg.NrCommitPorts-1:0][CAUSE_LEN-1:0] cause_itt;
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logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] tval_itt;
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logic [CVA6Cfg.NrCommitPorts-1:0][IRETIRE_LEN-1:0] counter;
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logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] addr;
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@ -94,38 +94,38 @@ module cva6_iti #(
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);
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// Adding this to ensure that interuption/exception happen only in commit port 0 of cva6
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assign cause_itt[i] = i==0 ? rvfi_to_iti_i.cause[CAUSE_LEN-1:0] : '0;
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assign tval_itt[i] = i==0 ? rvfi_to_iti_i.tval : '0;
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assign cause_itt[i] = i == 0 ? rvfi_to_iti_i.cause[CAUSE_LEN-1:0] : '0;
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assign tval_itt[i] = i == 0 ? rvfi_to_iti_i.tval : '0;
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// Systolic logic (First itt is connected to D Flip-Flop to continue computation if needed)
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assign counter_itt[i] = i==0 ? counter_q : counter[i-1];
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assign addr_itt[i] = i==0 ? addr_q : addr[i-1];
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assign special_itt[i] = i==0 ? special_q : special[i-1];
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assign counter_itt[i] = i == 0 ? counter_q : counter[i-1];
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assign addr_itt[i] = i == 0 ? addr_q : addr[i-1];
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assign special_itt[i] = i == 0 ? special_q : special[i-1];
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instr_to_trace #(
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.CVA6Cfg(CVA6Cfg),
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.uop_entry_t(uop_entry_t),
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.itt_out_t(itt_out_t),
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.CAUSE_LEN(CAUSE_LEN),
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.ITYPE_LEN(ITYPE_LEN),
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.IRETIRE_LEN(IRETIRE_LEN)
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instr_to_trace #(
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.CVA6Cfg(CVA6Cfg),
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.uop_entry_t(uop_entry_t),
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.itt_out_t(itt_out_t),
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.CAUSE_LEN(CAUSE_LEN),
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.ITYPE_LEN(ITYPE_LEN),
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.IRETIRE_LEN(IRETIRE_LEN)
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) i_instr_to_trace (
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.uop_entry_i(uop_entry[i]),
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.cause_i(cause_itt[i]),
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.tval_i(tval_itt[i]),
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.counter_i(counter_itt[i]),
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.iaddr_i(addr_itt[i]),
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.was_special_i(special_itt[i]),
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.itt_out_o(itt_out[i]),
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.counter_o(counter[i]),
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.iaddr_o(addr[i]),
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.is_special_o(special[i])
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.uop_entry_i(uop_entry[i]),
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.cause_i(cause_itt[i]),
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.tval_i(tval_itt[i]),
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.counter_i(counter_itt[i]),
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.iaddr_i(addr_itt[i]),
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.was_special_i(special_itt[i]),
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.itt_out_o(itt_out[i]),
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.counter_o(counter[i]),
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.iaddr_o(addr[i]),
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.is_special_o(special[i])
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);
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end
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always_comb begin
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iti_to_encoder_o.cause = '0;
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iti_to_encoder_o.tval = '0;
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iti_to_encoder_o.cause = '0;
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iti_to_encoder_o.tval = '0;
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for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
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uop_entry[i].valid = valid_i[i];
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uop_entry[i].pc = rvfi_to_iti_i.pc[i];
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@ -145,14 +145,14 @@ module cva6_iti #(
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iti_to_encoder_o.iretire[i] = itt_out[i].iretire;
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iti_to_encoder_o.ilastsize[i] = itt_out[i].ilastsize;
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iti_to_encoder_o.itype[i] = itt_out[i].itype;
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iti_to_encoder_o.iaddr[i]= itt_out[i].iaddr;
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iti_to_encoder_o.iaddr[i] = itt_out[i].iaddr;
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iti_to_encoder_o.priv = itt_out[i].priv; // privilege don't change between 2 instr comitted in the same cycle
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iti_to_encoder_o.cycles = itt_out[i].cycles; // Same here (same time at same cycle)
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iti_to_encoder_o.cycles = itt_out[i].cycles; // Same here (same time at same cycle)
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end
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end
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if (itt_out[0].valid) begin // interrupt & exception only in port 0
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iti_to_encoder_o.cause = itt_out[0].cause;
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iti_to_encoder_o.tval = itt_out[0].tval;
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if (itt_out[0].valid) begin // interrupt & exception only in port 0
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iti_to_encoder_o.cause = itt_out[0].cause;
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iti_to_encoder_o.tval = itt_out[0].tval;
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end
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end
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@ -170,15 +170,19 @@ module cva6_iti #(
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addr_q <= addr_d;
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special_q <= special_d;
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end
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//pragma translate_off
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//pragma translate_off
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for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
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if (itt_out[i].valid) begin
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$fwrite(f, "i :%d , val = %d , iret = %d, ilast = 0x%d , itype = %d , cause = 0x%h , tval= 0x%h , priv = 0x%d , iadd= 0x%h, time =%d \n",
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i, itt_out[i].valid, itt_out[i].iretire , itt_out[i].ilastsize , itt_out[i].itype , itt_out[i].cause, itt_out[i].tval, itt_out[i].priv , itt_out[i].iaddr , itt_out[i].cycles);
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$fwrite(
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f,
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"i :%d , val = %d , iret = %d, ilast = 0x%d , itype = %d , cause = 0x%h , tval= 0x%h , priv = 0x%d , iadd= 0x%h, time =%d \n",
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i, itt_out[i].valid, itt_out[i].iretire, itt_out[i].ilastsize, itt_out[i].itype,
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itt_out[i].cause, itt_out[i].tval, itt_out[i].priv, itt_out[i].iaddr,
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itt_out[i].cycles);
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end
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end
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//pragma translate_on
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end
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//pragma translate_on
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end
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endmodule
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endmodule
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@ -21,16 +21,15 @@
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it produces the type of the instruction
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*/
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module itype_detector
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#(
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parameter ITYPE_LEN = 3 //Size is itype_width_p in the E-Trace SPEC (3 or 4)
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)(
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input logic valid_i,
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input logic exception_i,
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input logic interrupt_i,
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input ariane_pkg::fu_op op_i,
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input logic branch_taken_i,
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output iti_pkg::itype_t itype_o
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module itype_detector #(
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parameter ITYPE_LEN = 3 //Size is itype_width_p in the E-Trace SPEC (3 or 4)
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) (
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input logic valid_i,
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input logic exception_i,
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input logic interrupt_i,
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input ariane_pkg::fu_op op_i,
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input logic branch_taken_i,
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output iti_pkg::itype_t itype_o
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);
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// internal signals
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@ -48,7 +47,7 @@ module itype_detector
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assign eret = op_i inside {ariane_pkg::MRET , ariane_pkg::SRET , ariane_pkg::DRET};
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assign eret = op_i inside {ariane_pkg::MRET, ariane_pkg::SRET, ariane_pkg::DRET};
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assign nontaken_branch = ( op_i == ariane_pkg::EQ ||
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op_i == ariane_pkg::NE ||
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@ -84,7 +83,7 @@ module itype_detector
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itype_o = iti_pkg::NON_TAKEN_BR;
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end else if (taken_branch) begin // taken branch
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itype_o = iti_pkg::TAKEN_BR;
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end else if (ITYPE_LEN == 3 && updiscon) begin // uninferable discontinuity
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end else if (ITYPE_LEN == 3 && updiscon) begin // uninferable discontinuity
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itype_o = iti_pkg::UNINF_JMP;
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end
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end
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@ -258,7 +258,7 @@ module cva6_rvfi
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logic [31:0] instr;
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logic branch_valid;
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logic is_taken;
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logic is_compressed;
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logic is_compressed;
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} sb_mem_t;
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sb_mem_t [CVA6Cfg.NR_SB_ENTRIES-1:0] mem_q, mem_n;
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@ -282,9 +282,9 @@ module cva6_rvfi
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end
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end
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if (branch_valid_iti) begin
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mem_n[branch_trans_id].branch_valid=branch_valid_iti;
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mem_n[branch_trans_id].is_taken=is_taken_iti;
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end
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mem_n[branch_trans_id].branch_valid = branch_valid_iti;
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mem_n[branch_trans_id].is_taken = is_taken_iti;
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end
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if (lsu_rmask != 0) begin
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mem_n[lsu_addr_trans_id].lsu_addr = lsu_addr;
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mem_n[lsu_addr_trans_id].lsu_rmask = lsu_rmask;
|
||||
|
|
@ -354,9 +354,9 @@ module cva6_rvfi
|
|||
rvfi_to_iti_o.branch_valid[i] <= mem_q[commit_pointer[i]].branch_valid;
|
||||
rvfi_to_iti_o.is_taken[i] <= mem_q[commit_pointer[i]].is_taken;
|
||||
rvfi_to_iti_o.is_compressed[i] <= mem_q[commit_pointer[i]].is_compressed;
|
||||
rvfi_to_iti_o.valid[i]<=valid_iti[i];
|
||||
rvfi_to_iti_o.pc[i]<=pc_iti[i];
|
||||
rvfi_to_iti_o.op[i]<=op_iti[i];
|
||||
rvfi_to_iti_o.valid[i] <= valid_iti[i];
|
||||
rvfi_to_iti_o.pc[i] <= pc_iti[i];
|
||||
rvfi_to_iti_o.op[i] <= op_iti[i];
|
||||
end
|
||||
rvfi_to_iti_o.ex_valid <= ex_commit_valid;
|
||||
rvfi_to_iti_o.cycles <= time_iti;
|
||||
|
|
|
|||
|
|
@ -10,9 +10,9 @@
|
|||
|
||||
package iti_pkg;
|
||||
|
||||
localparam CAUSE_LEN = 5; //Size is ecause_width_p in the E-Trace SPEC
|
||||
localparam ITYPE_LEN = 3; //Size is itype_width_p in the E-Trace SPEC (3 or 4)
|
||||
localparam IRETIRE_LEN = 32; //Size is iretire_width_p in the E-Trace SPEC
|
||||
localparam CAUSE_LEN = 5; //Size is ecause_width_p in the E-Trace SPEC
|
||||
localparam ITYPE_LEN = 3; //Size is itype_width_p in the E-Trace SPEC (3 or 4)
|
||||
localparam IRETIRE_LEN = 32; //Size is iretire_width_p in the E-Trace SPEC
|
||||
|
||||
typedef enum logic [ITYPE_LEN-1:0] {
|
||||
STANDARD = 0, // none of the other named itype codes
|
||||
|
|
@ -30,7 +30,7 @@ package iti_pkg;
|
|||
CRS = 12, // co-routine swap
|
||||
RET = 13, // return
|
||||
OUIJ = 14, // other uninferable jump
|
||||
OIJ = 15*/ // other inferable jump
|
||||
OIJ = 15*/ // other inferable jump
|
||||
} itype_t;
|
||||
|
||||
endpackage
|
||||
endpackage
|
||||
|
|
|
|||
|
|
@ -13,4 +13,4 @@
|
|||
logic [63:0] cycles; \
|
||||
}
|
||||
|
||||
`endif // ITI_TYPES_SVH
|
||||
`endif // ITI_TYPES_SVH
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue