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condition branch_unit and alu (#2342)

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Asmaa Kassimi 2024-07-10 10:02:18 +01:00 • committed by GitHub
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2 changed files with 6 additions and 4 deletions
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4
core/alu.sv
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@ -150,9 +150,9 @@ module alu
assign shift_amt = fu_data_i.operand_b;
assign shift_left = (fu_data_i.operation == SLL) | (fu_data_i.operation == SLLW);
assign shift_left = (fu_data_i.operation == SLL) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SLLW);
assign shift_arithmetic = (fu_data_i.operation == SRA) | (fu_data_i.operation == SRAW);
assign shift_arithmetic = (fu_data_i.operation == SRA) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SRAW);
// right shifts, we let the synthesizer optimize this
logic [CVA6Cfg.XLEN:0] shift_op_a_64;

6
core/branch_unit.sv
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@ -120,8 +120,10 @@ module branch_unit #(
branch_exception_o.gva = CVA6Cfg.RVH ? v_i : 1'b0;
// Only throw instruction address misaligned exception if this is indeed a `taken` conditional branch or
// an unconditional jump
if (branch_valid_i && (target_address[0] || (!CVA6Cfg.RVC && target_address[1])) && jump_taken) begin
branch_exception_o.valid = 1'b1;
if (!CVA6Cfg.RVC) begin
if (branch_valid_i && (target_address[0] || target_address[1]) && jump_taken) begin
branch_exception_o.valid = 1'b1;
end
end
end
endmodule