github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-22 21:27:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Fix access issues for reserved fields (#2187)

Browse source
This commit is contained in:
AbdessamiiOukalrazqou 2024-06-03 15:54:10 +02:00 • committed by GitHub
parent 1c828c0a16
commit e0da6e3569
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
13 changed files with 988 additions and 647 deletions
Download patch file Download diff file Expand all files Collapse all files

12
config/gen_from_riscv_config/README.md
View file

@ -53,10 +53,10 @@ python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_ge
You could find your output files in this directory :
if the output is ISA Documentation:
[Config_Name]\isa\
`<Config_Name>/isa/`
if the output is CSR Documentation :
[Config_Name]\csr\
`<Config_Name>/csr/`
for more details about How to write CSR or ISA Updater,see [UPDATERS](##Updaters) section
@ -86,7 +86,7 @@ If you want to add an extension to documentation not existed by default u can pu
- Format :
[Extension_Name]: True
<Extension_Name>: True
- Example :
@ -96,7 +96,7 @@ If you want to remove an extension from documentation not existed by default u c
- Format :
[Extension_Name]: False
<Extension_Name>: False
- Example :
@ -107,7 +107,7 @@ If you want to remove an extension from documentation already existed :
- Format :
[Extension_Name]: False
<Extension_Name>: False
- Example :
@ -191,7 +191,7 @@ Risc-V Config Yaml file is generated based on Risc-Config tool which include all
<https://github.com/openhwgroup/cva6/tree/master/vendor/riscv/riscv-config>.
You can execute the tool from `Config/riscv-config` repo :
You can execute the tool from `../config/riscv-config` repo :
- It needs python dependancies with :

325
config/gen_from_riscv_config/cv32a65x/csr/csr.md
View file

@ -12,349 +12,342 @@ Author: Abdessamii Oukalrazqou
|Address|Register Name|Description|
| :--- | :--- | :--- |
|0x300|[mstatus](#mstatus)|The mstatus register keeps track of and controls the hart’s current operating state.|
|0x300|[mstatush](#mstatush)|The mstatush register keeps track of and controls the hart’s current operating state.|
|0x301|[misa](#misa)|misa is a read-write register reporting the ISA supported by the hart.|
|0x304|[mie](#mie)|The mie register is an MXLEN-bit read/write register containing interrupt enable bits.|
|0x305|[mtvec](#mtvec)|MXLEN-bit read/write register that holds trap vector configuration.|
|0x320|[mcountinhibit](#mcountinhibit)|The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.|
|0x323-0x33f|[mhpmevent[3-31]](#mhpmevent[3-31])|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.|
|0x340|[mscratch](#mscratch)|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.|
|0x341|[mepc](#mepc)|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.|
|0x342|[mcause](#mcause)|The mcause register stores the information regarding the trap.|
|0x343|[mtval](#mtval)|The mtval is a warl register that holds the address of the instruction which caused the exception.|
|0x344|[mip](#mip)|The mip register is an MXLEN-bit read/write register containing information on pending interrupts.|
|0x3a0-0x3af|[pmpcfg[0-15]](#pmpcfg[0-15])|PMP configuration register|
|0x3b0-0x3ef|[pmpaddr[0-63]](#pmpaddr[0-63])|Physical memory protection address register|
|0xb00|[mcycle](#mcycle)|Counts the number of clock cycles executed from an arbitrary point in time.|
|0xb02|[minstret](#minstret)|Counts the number of instructions completed from an arbitrary point in time.|
|0xb03-0xb1f|[mhpmcounter[3-31]](#mhpmcounter[3-31])|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.|
|0xb80|[mcycleh](#mcycleh)|upper 32 bits of mcycle|
|0xb82|[minstreth](#minstreth)|Upper 32 bits of minstret.|
|0xb83-0xb9f|[mhpmcounter[3-31]h](#mhpmcounter[3-31]h)|The mhpmcounterh returns the upper half word in RV32I systems.|
|0xf11|[mvendorid](#mvendorid)||
|0xf12|[marchid](#marchid)|MXLEN-bit read-only register encoding the base microarchitecture of the hart.|
|0xf13|[mimpid](#mimpid)|Provides a unique encoding of the version of the processor implementation.|
|0xf14|[mhartid](#mhartid)|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.|
|0x300|[MSTATUS](#MSTATUS)|The mstatus register keeps track of and controls the hart’s current operating state.|
|0x300|[MSTATUSH](#MSTATUSH)|The mstatush register keeps track of and controls the hart’s current operating state.|
|0x301|[MISA](#MISA)|misa is a read-write register reporting the ISA supported by the hart.|
|0x304|[MIE](#MIE)|The mie register is an MXLEN-bit read/write register containing interrupt enable bits.|
|0x305|[MTVEC](#MTVEC)|MXLEN-bit read/write register that holds trap vector configuration.|
|0x323-0x33f|[MHPMEVENT[3-31]](#MHPMEVENT[3-31])|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.|
|0x340|[MSCRATCH](#MSCRATCH)|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.|
|0x341|[MEPC](#MEPC)|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.|
|0x342|[MCAUSE](#MCAUSE)|The mcause register stores the information regarding the trap.|
|0x343|[MTVAL](#MTVAL)|The mtval is a warl register that holds the address of the instruction which caused the exception.|
|0x344|[MIP](#MIP)|The mip register is an MXLEN-bit read/write register containing information on pending interrupts.|
|0x3a0-0x3a1|[PMPCFG[0-1]](#PMPCFG[0-1])|PMP configuration register|
|0x3b0-0x3b7|[PMPADDR[0-7]](#PMPADDR[0-7])|Physical memory protection address register|
|0xb00|[MCYCLE](#MCYCLE)|Counts the number of clock cycles executed from an arbitrary point in time.|
|0xb02|[MINSTRET](#MINSTRET)|Counts the number of instructions completed from an arbitrary point in time.|
|0xb03-0xb1f|[MHPMCOUNTER[3-31]](#MHPMCOUNTER[3-31])|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.|
|0xb80|[MCYCLEH](#MCYCLEH)|upper 32 bits of mcycle|
|0xb82|[MINSTRETH](#MINSTRETH)|Upper 32 bits of minstret.|
|0xb83-0xb9f|[MHPMCOUNTER[3-31]H](#MHPMCOUNTER[3-31]H)|The mhpmcounterh returns the upper half word in RV32I systems.|
|0xf11|[MVENDORID](#MVENDORID)|32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.|
|0xf12|[MARCHID](#MARCHID)|MXLEN-bit read-only register encoding the base microarchitecture of the hart.|
|0xf13|[MIMPID](#MIMPID)|Provides a unique encoding of the version of the processor implementation.|
|0xf14|[MHARTID](#MHARTID)|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.|
### Registers Description
#### mstatus
#### MSTATUS
---
**Address** 0x300
**Reset Value** 0x1800
**Privilege Mode** M
**Description** The mstatus register keeps track of and controls the hart’s current operating state.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|0|uie|||RW|Stores the state of the user mode interrupts.|
|1|sie|||RW|Stores the state of the supervisor mode interrupts.|
|3|mie|0|1|RW|Stores the state of the machine mode interrupts.|
|4|upie|||RW|Stores the state of the user mode interrupts prior to the trap.|
|5|spie|||RW|Stores the state of the supervisor mode interrupts prior to the trap.|
|7|mpie|0|1|RW|Stores the state of the machine mode interrupts prior to the trap.|
|8|spp|||RW|Stores the previous priority mode for supervisor.|
|[12:11]|mpp|0|3|RW|Stores the previous priority mode for machine.|
|[14:13]|fs|||RW|Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers.|
|[16:15]|xs|||RW|Encodes the status of additional user-mode extensions and associated state.|
|17|mprv|||RW|Modifies the privilege level at which loads and stores execute in all privilege modes.|
|18|sum|||RW|Modifies the privilege with which S-mode loads and stores access virtual memory.|
|19|mxr|||RW|Modifies the privilege with which loads access virtual memory.|
|20|tvm|||RW|Supports intercepting supervisor virtual-memory management operations.|
|21|tw|||RW|Supports intercepting the WFI instruction.|
|22|tsr|||RW|Supports intercepting the supervisor exception return instruction.|
|23|spelp|||RW|Supervisor mode previous expected-landing-pad (ELP) state.|
|31|sd|||RW|Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state.|
|[30:24]|Reserved_24|||Reserved|Reserved|
|0|UIE||0x0|WARL|Stores the state of the user mode interrupts.|
|1|SIE||0x0|WARL|Stores the state of the supervisor mode interrupts.|
|2|RESERVED_2||0x0|WPRI|RESERVED|
|3|MIE|[0 , 1]|0x0|WLRL|Stores the state of the machine mode interrupts.|
|4|UPIE||0x0|WARL|Stores the state of the user mode interrupts prior to the trap.|
|5|SPIE||0x0|WARL|Stores the state of the supervisor mode interrupts prior to the trap.|
|6|RESERVED_6||0x0|WPRI|RESERVED|
|7|MPIE|[0 , 1]|0x0|WLRL|Stores the state of the machine mode interrupts prior to the trap.|
|8|SPP||0x0|WARL|Stores the previous priority mode for supervisor.|
|[10:9]|RESERVED_9||0x0|WPRI|RESERVED|
|[12:11]|MPP|[0x3]|0x3|WARL|Stores the previous priority mode for machine.|
|[14:13]|FS||0x0|WARL|Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers.|
|[16:15]|XS||0x0|WARL|Encodes the status of additional user-mode extensions and associated state.|
|17|MPRV||0x0|WARL|Modifies the privilege level at which loads and stores execute in all privilege modes.|
|18|SUM||0x0|WARL|Modifies the privilege with which S-mode loads and stores access virtual memory.|
|19|MXR||0x0|WARL|Modifies the privilege with which loads access virtual memory.|
|20|TVM||0x0|WARL|Supports intercepting supervisor virtual-memory management operations.|
|21|TW||0x0|WARL|Supports intercepting the WFI instruction.|
|22|TSR||0x0|WARL|Supports intercepting the supervisor exception return instruction.|
|23|SPELP||0x0|WARL|Supervisor mode previous expected-landing-pad (ELP) state.|
|[30:24]|RESERVED_24||0x0|WPRI|RESERVED|
|31|SD||0x0|WARL|Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state.|
#### mstatush
#### MSTATUSH
---
**Address** 0x300
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mstatush register keeps track of and controls the hart’s current operating state.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|4|sbe|||RW|control the endianness of memory accesses other than instruction fetches for supervisor mode|
|5|mbe|||RW|control the endianness of memory accesses other than instruction fetches for machine mode|
|6|gva|||RW|Stores the state of the supervisor mode interrupts.|
|7|mpv|||RW|Stores the state of the user mode interrupts.|
|9|mpelp|||RW|Machine mode previous expected-landing-pad (ELP) state.|
|[31:10]|Reserved_10|||Reserved|Reserved|
|[3:0]|RESERVED_0||0x0|WPRI|RESERVED|
|4|SBE||0x0|WARL|control the endianness of memory accesses other than instruction fetches for supervisor mode|
|5|MBE||0x0|WARL|control the endianness of memory accesses other than instruction fetches for machine mode|
|6|GVA||0x0|WARL|Stores the state of the supervisor mode interrupts.|
|7|MPV||0x0|WARL|Stores the state of the user mode interrupts.|
|8|RESERVED_8||0x0|WPRI|RESERVED|
|9|MPELP||0x0|WARL|Machine mode previous expected-landing-pad (ELP) state.|
|[31:10]|RESERVED_10||0x0|WPRI|RESERVED|
#### misa
#### MISA
---
**Address** 0x301
**Reset Value** 0x40001104
**Reset Value** 0x40001106
**Privilege Mode** M
**Description** misa is a read-write register reporting the ISA supported by the hart.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[25:0]|extensions|0x0000000|0x3FFFFFF|RW|Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.|
|[31:30]|mxl|0|1||Encodes the native base integer ISA width.|
|[29:26]|Reserved_26|||Reserved|Reserved|
|[25:0]|EXTENSIONS|[0x0000000:0x3FFFFFF]|0x1106|WARL|Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.|
|[29:26]|RESERVED_26||0x0|WPRI|RESERVED|
|[31:30]|MXL|[0x1]|0x1|WARL|Encodes the native base integer ISA width.|
#### mie
#### MIE
---
**Address** 0x304
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mie register is an MXLEN-bit read/write register containing interrupt enable bits.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|0|usie|||RW|User Software Interrupt enable.|
|1|ssie|||RW|Supervisor Software Interrupt enable.|
|2|vssie|||RW|VS-level Software Interrupt enable.|
|3|msie|0x0|0x1|RW|Machine Software Interrupt enable.|
|4|utie|||RW|User Timer Interrupt enable.|
|5|stie|||RW|Supervisor Timer Interrupt enable.|
|6|vstie|||RW|VS-level Timer Interrupt enable.|
|7|mtie|0|1|RW|Machine Timer Interrupt enable.|
|8|ueie|||RW|User External Interrupt enable.|
|9|seie|||RW|Supervisor External Interrupt enable.|
|10|vseie|||RW|VS-level External Interrupt enable.|
|11|meie|0|1|RW|Machine External Interrupt enable.|
|12|sgeie|||RW|HS-level External Interrupt enable.|
|[31:13]|Reserved_13|||Reserved|Reserved|
|0|USIE||0x0|WARL|User Software Interrupt enable.|
|1|SSIE||0x0|WARL|Supervisor Software Interrupt enable.|
|2|VSSIE||0x0|WARL|VS-level Software Interrupt enable.|
|3|MSIE|[0x0 , 0x1]|0x0|WLRL|Machine Software Interrupt enable.|
|4|UTIE||0x0|WARL|User Timer Interrupt enable.|
|5|STIE||0x0|WARL|Supervisor Timer Interrupt enable.|
|6|VSTIE||0x0|WARL|VS-level Timer Interrupt enable.|
|7|MTIE|[0 , 1]|0x0|WLRL|Machine Timer Interrupt enable.|
|8|UEIE||0x0|WARL|User External Interrupt enable.|
|9|SEIE||0x0|WARL|Supervisor External Interrupt enable.|
|10|VSEIE||0x0|WARL|VS-level External Interrupt enable.|
|11|MEIE|[0 , 1]|0x0|WLRL|Machine External Interrupt enable.|
|12|SGEIE||0x0|WARL|HS-level External Interrupt enable.|
|[31:13]|RESERVED_13||0x0|WPRI|RESERVED|
#### mtvec
#### MTVEC
---
**Address** 0x305
**Reset Value** 0x80010000
**Privilege Mode** M
**Description** MXLEN-bit read/write register that holds trap vector configuration.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[1:0]|mode|0|0|RW|Vector mode.|
|[31:2]|base|0x3FFFFFFF|0x00000000|RW|Vector base address.|
|[1:0]|MODE|[0x0]|0x0|WARL|Vector mode.|
|[31:2]|BASE|[0x3FFFFFFF, 0x00000000]|0x20004000|WARL|Vector base address.|
#### mcountinhibit
---
**Address** 0x320
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.
|Bits|Field Name|Legal Values|Mask|Access|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mcountinhibit|0x00000000|0xFFFFFFFF|RW|The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.|
#### mhpmevent[3-31]
#### MHPMEVENT[3-31]
---
**Address** 0x323-0x33f
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mhpmevent[i]|0x00000000|0xFFFFFFFF|RW|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.|
|[31:0]|MHPMEVENT[I]|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.|
#### mscratch
#### MSCRATCH
---
**Address** 0x340
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mscratch|0x00000000|0xFFFFFFFF|RW|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.|
|[31:0]|MSCRATCH|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.|
#### mepc
#### MEPC
---
**Address** 0x341
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mepc is a warl register that must be able to hold all valid physical and virtual addresses.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mepc|0x00000000|0xFFFFFFFF|RW|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.|
|[31:0]|MEPC|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.|
#### mcause
#### MCAUSE
---
**Address** 0x342
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mcause register stores the information regarding the trap.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[30:0]|exception_code|0|15|RW|Encodes the exception code.|
|31|interrupt|0x0|0x1|RW|Indicates whether the trap was due to an interrupt.|
|[30:0]|EXCEPTION_CODE|[0 , 15]|0x0|WLRL|Encodes the exception code.|
|31|INTERRUPT|[0x0 , 0x1]|0x0|WLRL|Indicates whether the trap was due to an interrupt.|
#### mtval
#### MTVAL
---
**Address** 0x343
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mtval is a warl register that holds the address of the instruction which caused the exception.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mtval|0x00000000|0xFFFFFFFF|RW|The mtval is a warl register that holds the address of the instruction which caused the exception.|
|[31:0]|MTVAL|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mtval is a warl register that holds the address of the instruction which caused the exception.|
#### mip
#### MIP
---
**Address** 0x344
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mip register is an MXLEN-bit read/write register containing information on pending interrupts.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|0|usip|||RW|User Software Interrupt Pending.|
|1|ssip|||RW|Supervisor Software Interrupt Pending.|
|2|vssip|||RW|VS-level Software Interrupt Pending.|
|3|msip|0x1|0|RW|Machine Software Interrupt Pending.|
|4|utip|||RW|User Timer Interrupt Pending.|
|5|stip|||RW|Supervisor Timer Interrupt Pending.|
|6|vstip|||RW|VS-level Timer Interrupt Pending.|
|7|mtip|0x1|0|RW|Machine Timer Interrupt Pending.|
|8|ueip|||RW|User External Interrupt Pending.|
|9|seip|||RW|Supervisor External Interrupt Pending.|
|10|vseip|||RW|VS-level External Interrupt Pending.|
|11|meip|0x1|0|RW|Machine External Interrupt Pending.|
|12|sgeip|||RW|HS-level External Interrupt Pending.|
|[31:13]|Reserved_13|||Reserved|Reserved|
|0|USIP||0x0|WARL|User Software Interrupt Pending.|
|1|SSIP||0x0|WARL|Supervisor Software Interrupt Pending.|
|2|VSSIP||0x0|WARL|VS-level Software Interrupt Pending.|
|3|MSIP|0x1|0x0|RO_VARIABLE|Machine Software Interrupt Pending.|
|4|UTIP||0x0|WARL|User Timer Interrupt Pending.|
|5|STIP||0x0|WARL|Supervisor Timer Interrupt Pending.|
|6|VSTIP||0x0|WARL|VS-level Timer Interrupt Pending.|
|7|MTIP|0x1|0x0|RO_VARIABLE|Machine Timer Interrupt Pending.|
|8|UEIP||0x0|WARL|User External Interrupt Pending.|
|9|SEIP||0x0|WARL|Supervisor External Interrupt Pending.|
|10|VSEIP||0x0|WARL|VS-level External Interrupt Pending.|
|11|MEIP|0x1|0x0|RO_VARIABLE|Machine External Interrupt Pending.|
|12|SGEIP||0x0|WARL|HS-level External Interrupt Pending.|
|[31:13]|RESERVED_13||0x0|WPRI|RESERVED|
#### pmpcfg[0-15]
#### PMPCFG[0-1]
---
**Address** 0x3a0-0x3af
**Address** 0x3a0-0x3a1
**Reset Value** 0x0
**Privilege Mode** M
**Description** PMP configuration register
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[7:0]|pmp[i*4 + 0]cfg|0x00|0xFF|RW|pmp configuration bits|
|[15:8]|pmp[i*4 + 1]cfg|0x00|0xFF|RW|pmp configuration bits|
|[23:16]|pmp[i*4 + 2]cfg|0x00|0xFF|RW|pmp configuration bits|
|[31:24]|pmp[i*4 + 3]cfg|0x00|0xFF|RW|pmp configuration bits|
|[7:0]|PMP[I*4 + 0]CFG|[0x00:0xFF]|0x0|WARL|pmp configuration bits|
|[15:8]|PMP[I*4 + 1]CFG|[0x00:0xFF]|0x0|WARL|pmp configuration bits|
|[23:16]|PMP[I*4 + 2]CFG|[0x00:0xFF]|0x0|WARL|pmp configuration bits|
|[31:24]|PMP[I*4 + 3]CFG|[0x00:0xFF]|0x0|WARL|pmp configuration bits|
#### pmpaddr[0-63]
#### PMPADDR[0-7]
---
**Address** 0x3b0-0x3ef
**Reset Value** 0x20
**Address** 0x3b0-0x3b7
**Reset Value** 0x0
**Privilege Mode** M
**Description** Physical memory protection address register
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|pmpaddr[i]|0x00000000|0xFFFFFFFF|RW|Physical memory protection address register|
|[31:0]|PMPADDR[I]|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|Physical memory protection address register|
#### mcycle
#### MCYCLE
---
**Address** 0xb00
**Reset Value** 0x1e253
**Reset Value** 0x0
**Privilege Mode** M
**Description** Counts the number of clock cycles executed from an arbitrary point in time.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mcycle|0x00000000|0xFFFFFFFF|RW|Counts the number of clock cycles executed from an arbitrary point in time.|
|[31:0]|MCYCLE|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|Counts the number of clock cycles executed from an arbitrary point in time.|
#### minstret
#### MINSTRET
---
**Address** 0xb02
**Reset Value** 0x0
**Privilege Mode** M
**Description** Counts the number of instructions completed from an arbitrary point in time.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|minstret|0x00000000|0xFFFFFFFF|RW|Counts the number of instructions completed from an arbitrary point in time.|
|[31:0]|MINSTRET|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|Counts the number of instructions completed from an arbitrary point in time.|
#### mhpmcounter[3-31]
#### MHPMCOUNTER[3-31]
---
**Address** 0xb03-0xb1f
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mhpmcounter[i]|0x00000000|0xFFFFFFFF|RW|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.|
|[31:0]|MHPMCOUNTER[I]|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.|
#### mcycleh
#### MCYCLEH
---
**Address** 0xb80
**Reset Value** 0x0
**Privilege Mode** M
**Description** upper 32 bits of mcycle
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mcycleh|0x00000000|0xFFFFFFFF|RW|upper 32 bits of mcycle|
|[31:0]|MCYCLEH|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|upper 32 bits of mcycle|
#### minstreth
#### MINSTRETH
---
**Address** 0xb82
**Reset Value** 0x0
**Privilege Mode** M
**Description** Upper 32 bits of minstret.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|minstreth|0x00000000|0xFFFFFFFF|RW|Upper 32 bits of minstret.|
|[31:0]|MINSTRETH|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|Upper 32 bits of minstret.|
#### mhpmcounter[3-31]h
#### MHPMCOUNTER[3-31]H
---
**Address** 0xb83-0xb9f
**Reset Value** 0x0
**Privilege Mode** M
**Description** The mhpmcounterh returns the upper half word in RV32I systems.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mhpmcounter[i]h|0x00000000|0xFFFFFFFF|RW|The mhpmcounterh returns the upper half word in RV32I systems.|
|[31:0]|MHPMCOUNTER[I]H|[0x00000000 , 0xFFFFFFFF]|0x00000000|WARL|The mhpmcounterh returns the upper half word in RV32I systems.|
#### mvendorid
#### MVENDORID
---
**Address** 0xf11
**Reset Value** 0x602
**Privilege Mode** M
**Description**
|Bits|Field Name|Legal Values|Mask|Access|Description|
**Description** 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mvendorid|0x602|0|RW||
|[31:0]|MVENDORID|0x00000602|0x00000602|RO_CONSTANT|32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.|
#### marchid
#### MARCHID
---
**Address** 0xf12
**Reset Value** 0x3
**Privilege Mode** M
**Description** MXLEN-bit read-only register encoding the base microarchitecture of the hart.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|marchid|0x3|0|RW|MXLEN-bit read-only register encoding the base microarchitecture of the hart.|
|[31:0]|MARCHID|0x00000003|0x00000003|RO_CONSTANT|MXLEN-bit read-only register encoding the base microarchitecture of the hart.|
#### mimpid
#### MIMPID
---
**Address** 0xf13
**Reset Value** 0x0
**Privilege Mode** M
**Description** Provides a unique encoding of the version of the processor implementation.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mimpid|0x0|0|RW|Provides a unique encoding of the version of the processor implementation.|
|[31:0]|MIMPID|0x00000000|0x00000000|RO_CONSTANT|Provides a unique encoding of the version of the processor implementation.|
#### mhartid
#### MHARTID
---
**Address** 0xf14
**Reset Value** 0x0
**Privilege Mode** M
**Description** MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.
|Bits|Field Name|Legal Values|Mask|Access|Description|
|Bits|Field Name|Legal Values|Reset|Type|Description|
| :--- | :--- | :--- | :--- | :--- | :--- |
|[31:0]|mhartid|0x0|0|RW|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.|
|[31:0]|MHARTID|0x00000000|0x00000000|RO_CONSTANT|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.|

642
config/gen_from_riscv_config/cv32a65x/csr/csr.rst
View file

@ -12,61 +12,59 @@ csr
Register Summary
----------------
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| Address | Register Name | Description |
+=============+====================+============================================================================================================================+
| 0x300 | mstatus | The mstatus register keeps track of and controls the hart’s current operating state. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x300 | mstatush | The mstatush register keeps track of and controls the hart’s current operating state. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x301 | misa | misa is a read-write register reporting the ISA supported by the hart. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x304 | mie | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x305 | mtvec | MXLEN-bit read/write register that holds trap vector configuration. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x320 | mcountinhibit | The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x323-0x33f | mhpmevent[3-31] | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x340 | mscratch | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x341 | mepc | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x342 | mcause | The mcause register stores the information regarding the trap. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x343 | mtval | The mtval is a warl register that holds the address of the instruction which caused the exception. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x344 | mip | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x3a0-0x3af | pmpcfg[0-15] | PMP configuration register |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0x3b0-0x3ef | pmpaddr[0-63] | Physical memory protection address register |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xb00 | mcycle | Counts the number of clock cycles executed from an arbitrary point in time. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xb02 | minstret | Counts the number of instructions completed from an arbitrary point in time. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xb03-0xb1f | mhpmcounter[3-31] | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xb80 | mcycleh | upper 32 bits of mcycle |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xb82 | minstreth | Upper 32 bits of minstret. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xb83-0xb9f | mhpmcounter[3-31]h | The mhpmcounterh returns the upper half word in RV32I systems. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xf11 | mvendorid | |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xf12 | marchid | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xf13 | mimpid | Provides a unique encoding of the version of the processor implementation. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
| 0xf14 | mhartid | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| Address | Register Name | Description |
+=============+====================+====================================================================================================+
| 0x300 | MSTATUS | The mstatus register keeps track of and controls the hart’s current operating state. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x300 | MSTATUSH | The mstatush register keeps track of and controls the hart’s current operating state. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x301 | MISA | misa is a read-write register reporting the ISA supported by the hart. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x304 | MIE | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x305 | MTVEC | MXLEN-bit read/write register that holds trap vector configuration. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x323-0x33f | MHPMEVENT[3-31] | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x340 | MSCRATCH | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x341 | MEPC | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x342 | MCAUSE | The mcause register stores the information regarding the trap. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x343 | MTVAL | The mtval is a warl register that holds the address of the instruction which caused the exception. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x344 | MIP | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x3a0-0x3a1 | PMPCFG[0-1] | PMP configuration register |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0x3b0-0x3b7 | PMPADDR[0-7] | Physical memory protection address register |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xb00 | MCYCLE | Counts the number of clock cycles executed from an arbitrary point in time. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xb02 | MINSTRET | Counts the number of instructions completed from an arbitrary point in time. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xb03-0xb1f | MHPMCOUNTER[3-31] | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xb80 | MCYCLEH | upper 32 bits of mcycle |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xb82 | MINSTRETH | Upper 32 bits of minstret. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xb83-0xb9f | MHPMCOUNTER[3-31]H | The mhpmcounterh returns the upper half word in RV32I systems. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xf11 | MVENDORID | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xf12 | MARCHID | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xf13 | MIMPID | Provides a unique encoding of the version of the processor implementation. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
| 0xf14 | MHARTID | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
+-------------+--------------------+----------------------------------------------------------------------------------------------------+
Register Description
--------------------
mstatus
MSTATUS
-------
:Address: 0x300
@ -75,49 +73,55 @@ mstatus
:Description: The mstatus register keeps track of and controls the
hart’s current operating state.
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+=========+==============+================+========+==========+=================================================================================================================+
| 0 | uie | | | RW | Stores the state of the user mode interrupts. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 1 | sie | | | RW | Stores the state of the supervisor mode interrupts. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 3 | mie | 0 | 1 | RW | Stores the state of the machine mode interrupts. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 4 | upie | | | RW | Stores the state of the user mode interrupts prior to the trap. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 5 | spie | | | RW | Stores the state of the supervisor mode interrupts prior to the trap. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 7 | mpie | 0 | 1 | RW | Stores the state of the machine mode interrupts prior to the trap. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 8 | spp | | | RW | Stores the previous priority mode for supervisor. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| [12:11] | mpp | 0 | 3 | RW | Stores the previous priority mode for machine. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| [14:13] | fs | | | RW | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| [16:15] | xs | | | RW | Encodes the status of additional user-mode extensions and associated state. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 17 | mprv | | | RW | Modifies the privilege level at which loads and stores execute in all privilege modes. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 18 | sum | | | RW | Modifies the privilege with which S-mode loads and stores access virtual memory. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 19 | mxr | | | RW | Modifies the privilege with which loads access virtual memory. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 20 | tvm | | | RW | Supports intercepting supervisor virtual-memory management operations. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 21 | tw | | | RW | Supports intercepting the WFI instruction. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 22 | tsr | | | RW | Supports intercepting the supervisor exception return instruction. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 23 | spelp | | | RW | Supervisor mode previous expected-landing-pad (ELP) state. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| 31 | sd | | | RW | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
| [30:24] | Reserved_24 | | | Reserved | Reserved |
+---------+--------------+----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+=========+==============+================+=========+========+=================================================================================================================+
| 0 | UIE | | 0x0 | WARL | Stores the state of the user mode interrupts. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 1 | SIE | | 0x0 | WARL | Stores the state of the supervisor mode interrupts. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 2 | RESERVED_2 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 3 | MIE | [0 , 1] | 0x0 | WLRL | Stores the state of the machine mode interrupts. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 4 | UPIE | | 0x0 | WARL | Stores the state of the user mode interrupts prior to the trap. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 5 | SPIE | | 0x0 | WARL | Stores the state of the supervisor mode interrupts prior to the trap. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 6 | RESERVED_6 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 7 | MPIE | [0 , 1] | 0x0 | WLRL | Stores the state of the machine mode interrupts prior to the trap. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 8 | SPP | | 0x0 | WARL | Stores the previous priority mode for supervisor. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| [10:9] | RESERVED_9 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| [12:11] | MPP | [0x3] | 0x3 | WARL | Stores the previous priority mode for machine. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| [14:13] | FS | | 0x0 | WARL | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| [16:15] | XS | | 0x0 | WARL | Encodes the status of additional user-mode extensions and associated state. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 17 | MPRV | | 0x0 | WARL | Modifies the privilege level at which loads and stores execute in all privilege modes. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 18 | SUM | | 0x0 | WARL | Modifies the privilege with which S-mode loads and stores access virtual memory. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 19 | MXR | | 0x0 | WARL | Modifies the privilege with which loads access virtual memory. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 20 | TVM | | 0x0 | WARL | Supports intercepting supervisor virtual-memory management operations. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 21 | TW | | 0x0 | WARL | Supports intercepting the WFI instruction. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 22 | TSR | | 0x0 | WARL | Supports intercepting the supervisor exception return instruction. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 23 | SPELP | | 0x0 | WARL | Supervisor mode previous expected-landing-pad (ELP) state. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| [30:24] | RESERVED_24 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
| 31 | SD | | 0x0 | WARL | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. |
+---------+--------------+----------------+---------+--------+-----------------------------------------------------------------------------------------------------------------+
mstatush
MSTATUSH
--------
:Address: 0x300
@ -126,42 +130,46 @@ mstatush
:Description: The mstatush register keeps track of and controls the
hart’s current operating state.
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+=========+==============+================+========+==========+==============================================================================================+
| 4 | sbe | | | RW | control the endianness of memory accesses other than instruction fetches for supervisor mode |
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
| 5 | mbe | | | RW | control the endianness of memory accesses other than instruction fetches for machine mode |
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
| 6 | gva | | | RW | Stores the state of the supervisor mode interrupts. |
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
| 7 | mpv | | | RW | Stores the state of the user mode interrupts. |
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
| 9 | mpelp | | | RW | Machine mode previous expected-landing-pad (ELP) state. |
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
| [31:10] | Reserved_10 | | | Reserved | Reserved |
+---------+--------------+----------------+--------+----------+----------------------------------------------------------------------------------------------+
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+=========+==============+================+=========+========+==============================================================================================+
| [3:0] | RESERVED_0 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| 4 | SBE | | 0x0 | WARL | control the endianness of memory accesses other than instruction fetches for supervisor mode |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| 5 | MBE | | 0x0 | WARL | control the endianness of memory accesses other than instruction fetches for machine mode |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| 6 | GVA | | 0x0 | WARL | Stores the state of the supervisor mode interrupts. |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| 7 | MPV | | 0x0 | WARL | Stores the state of the user mode interrupts. |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| 8 | RESERVED_8 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| 9 | MPELP | | 0x0 | WARL | Machine mode previous expected-landing-pad (ELP) state. |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
| [31:10] | RESERVED_10 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+----------------------------------------------------------------------------------------------+
misa
MISA
----
:Address: 0x301
:Reset Value: 0x40001104
:Reset Value: 0x40001106
:Privilege Mode: M
:Description: misa is a read-write register reporting the ISA supported
by the hart.
+---------+--------------+----------------+-----------+----------+------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+=========+==============+================+===========+==========+================================================================================================+
| [25:0] | extensions | 0x0000000 | 0x3FFFFFF | RW | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. |
+---------+--------------+----------------+-----------+----------+------------------------------------------------------------------------------------------------+
| [31:30] | mxl | 0 | 1 | | Encodes the native base integer ISA width. |
+---------+--------------+----------------+-----------+----------+------------------------------------------------------------------------------------------------+
| [29:26] | Reserved_26 | | | Reserved | Reserved |
+---------+--------------+----------------+-----------+----------+------------------------------------------------------------------------------------------------+
+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+=========+==============+=======================+=========+========+================================================================================================+
| [25:0] | EXTENSIONS | [0x0000000:0x3FFFFFF] | 0x1106 | WARL | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. |
+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+
| [29:26] | RESERVED_26 | | 0x0 | WPRI | RESERVED |
+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+
| [31:30] | MXL | [0x1] | 0x1 | WARL | Encodes the native base integer ISA width. |
+---------+--------------+-----------------------+---------+--------+------------------------------------------------------------------------------------------------+
mie
MIE
---
:Address: 0x304
@ -170,39 +178,39 @@ mie
:Description: The mie register is an MXLEN-bit read/write register
containing interrupt enable bits.
+---------+--------------+----------------+--------+----------+---------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+=========+==============+================+========+==========+=======================================+
| 0 | usie | | | RW | User Software Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 1 | ssie | | | RW | Supervisor Software Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 2 | vssie | | | RW | VS-level Software Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 3 | msie | 0x0 | 0x1 | RW | Machine Software Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 4 | utie | | | RW | User Timer Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 5 | stie | | | RW | Supervisor Timer Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 6 | vstie | | | RW | VS-level Timer Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 7 | mtie | 0 | 1 | RW | Machine Timer Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 8 | ueie | | | RW | User External Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 9 | seie | | | RW | Supervisor External Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 10 | vseie | | | RW | VS-level External Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 11 | meie | 0 | 1 | RW | Machine External Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| 12 | sgeie | | | RW | HS-level External Interrupt enable. |
+---------+--------------+----------------+--------+----------+---------------------------------------+
| [31:13] | Reserved_13 | | | Reserved | Reserved |
+---------+--------------+----------------+--------+----------+---------------------------------------+
+---------+--------------+----------------+---------+--------+---------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+=========+==============+================+=========+========+=======================================+
| 0 | USIE | | 0x0 | WARL | User Software Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 1 | SSIE | | 0x0 | WARL | Supervisor Software Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 2 | VSSIE | | 0x0 | WARL | VS-level Software Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 3 | MSIE | [0x0 , 0x1] | 0x0 | WLRL | Machine Software Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 4 | UTIE | | 0x0 | WARL | User Timer Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 5 | STIE | | 0x0 | WARL | Supervisor Timer Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 6 | VSTIE | | 0x0 | WARL | VS-level Timer Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 7 | MTIE | [0 , 1] | 0x0 | WLRL | Machine Timer Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 8 | UEIE | | 0x0 | WARL | User External Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 9 | SEIE | | 0x0 | WARL | Supervisor External Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 10 | VSEIE | | 0x0 | WARL | VS-level External Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 11 | MEIE | [0 , 1] | 0x0 | WLRL | Machine External Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| 12 | SGEIE | | 0x0 | WARL | HS-level External Interrupt enable. |
+---------+--------------+----------------+---------+--------+---------------------------------------+
| [31:13] | RESERVED_13 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+--------+---------------------------------------+
mtvec
MTVEC
-----
:Address: 0x305
@ -211,30 +219,15 @@ mtvec
:Description: MXLEN-bit read/write register that holds trap vector
configuration.
+--------+--------------+----------------+------------+----------+----------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+======================+
| [1:0] | mode | 0 | 0 | RW | Vector mode. |
+--------+--------------+----------------+------------+----------+----------------------+
| [31:2] | base | 0x3FFFFFFF | 0x00000000 | RW | Vector base address. |
+--------+--------------+----------------+------------+----------+----------------------+
+--------+--------------+--------------------------+------------+--------+----------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+==========================+============+========+======================+
| [1:0] | MODE | [0x0] | 0x0 | WARL | Vector mode. |
+--------+--------------+--------------------------+------------+--------+----------------------+
| [31:2] | BASE | [0x3FFFFFFF, 0x00000000] | 0x20004000 | WARL | Vector base address. |
+--------+--------------+--------------------------+------------+--------+----------------------+
mcountinhibit
-------------
:Address: 0x320
:Reset Value: 0x00000000
:Privilege Mode: M
:Description: The mcountinhibit is a 32-bit WARL register that controls
which of the hardware performance-monitoring counters increment.
+--------+---------------+----------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+===============+================+============+==========+============================================================================================================================+
| [31:0] | mcountinhibit | 0x00000000 | 0xFFFFFFFF | RW | The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
+--------+---------------+----------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------+
mhpmevent[3-31]
MHPMEVENT[3-31]
---------------
:Address: 0x323-0x33f
@ -243,13 +236,13 @@ mhpmevent[3-31]
:Description: The mhpmevent is a MXLEN-bit event register which controls
mhpmcounter3.
+--------+--------------+----------------+------------+----------+--------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+==========================================================================+
| [31:0] | mhpmevent[i] | 0x00000000 | 0xFFFFFFFF | RW | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
+--------+--------------+----------------+------------+----------+--------------------------------------------------------------------------+
+--------+--------------+---------------------------+------------+--------+--------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+==========================================================================+
| [31:0] | MHPMEVENT[I] | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
+--------+--------------+---------------------------+------------+--------+--------------------------------------------------------------------------+
mscratch
MSCRATCH
--------
:Address: 0x340
@ -258,13 +251,13 @@ mscratch
:Description: The mscratch register is an MXLEN-bit read/write register
dedicated for use by machine mode.
+--------+--------------+----------------+------------+----------+----------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+==============================================================================================+
| [31:0] | mscratch | 0x00000000 | 0xFFFFFFFF | RW | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
+--------+--------------+----------------+------------+----------+----------------------------------------------------------------------------------------------+
+--------+--------------+---------------------------+------------+--------+----------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+==============================================================================================+
| [31:0] | MSCRATCH | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
+--------+--------------+---------------------------+------------+--------+----------------------------------------------------------------------------------------------+
mepc
MEPC
----
:Address: 0x341
@ -273,13 +266,13 @@ mepc
:Description: The mepc is a warl register that must be able to hold all
valid physical and virtual addresses.
+--------+--------------+----------------+------------+----------+-------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+=================================================================================================+
| [31:0] | mepc | 0x00000000 | 0xFFFFFFFF | RW | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. |
+--------+--------------+----------------+------------+----------+-------------------------------------------------------------------------------------------------+
+--------+--------------+---------------------------+------------+--------+-------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+=================================================================================================+
| [31:0] | MEPC | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. |
+--------+--------------+---------------------------+------------+--------+-------------------------------------------------------------------------------------------------+
mcause
MCAUSE
------
:Address: 0x342
@ -288,15 +281,15 @@ mcause
:Description: The mcause register stores the information regarding the
trap.
+--------+----------------+----------------+--------+----------+-----------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+================+================+========+==========+=====================================================+
| [30:0] | exception_code | 0 | 15 | RW | Encodes the exception code. |
+--------+----------------+----------------+--------+----------+-----------------------------------------------------+
| 31 | interrupt | 0x0 | 0x1 | RW | Indicates whether the trap was due to an interrupt. |
+--------+----------------+----------------+--------+----------+-----------------------------------------------------+
+--------+----------------+----------------+---------+--------+-----------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+================+================+=========+========+=====================================================+
| [30:0] | EXCEPTION_CODE | [0 , 15] | 0x0 | WLRL | Encodes the exception code. |
+--------+----------------+----------------+---------+--------+-----------------------------------------------------+
| 31 | INTERRUPT | [0x0 , 0x1] | 0x0 | WLRL | Indicates whether the trap was due to an interrupt. |
+--------+----------------+----------------+---------+--------+-----------------------------------------------------+
mtval
MTVAL
-----
:Address: 0x343
@ -305,13 +298,13 @@ mtval
:Description: The mtval is a warl register that holds the address of the
instruction which caused the exception.
+--------+--------------+----------------+------------+----------+----------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+====================================================================================================+
| [31:0] | mtval | 0x00000000 | 0xFFFFFFFF | RW | The mtval is a warl register that holds the address of the instruction which caused the exception. |
+--------+--------------+----------------+------------+----------+----------------------------------------------------------------------------------------------------+
+--------+--------------+---------------------------+------------+--------+----------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+====================================================================================================+
| [31:0] | MTVAL | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mtval is a warl register that holds the address of the instruction which caused the exception. |
+--------+--------------+---------------------------+------------+--------+----------------------------------------------------------------------------------------------------+
mip
MIP
---
:Address: 0x344
@ -320,88 +313,88 @@ mip
:Description: The mip register is an MXLEN-bit read/write register
containing information on pending interrupts.
+---------+--------------+----------------+--------+----------+----------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+=========+==============+================+========+==========+========================================+
| 0 | usip | | | RW | User Software Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 1 | ssip | | | RW | Supervisor Software Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 2 | vssip | | | RW | VS-level Software Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 3 | msip | 0x1 | 0 | RW | Machine Software Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 4 | utip | | | RW | User Timer Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 5 | stip | | | RW | Supervisor Timer Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 6 | vstip | | | RW | VS-level Timer Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 7 | mtip | 0x1 | 0 | RW | Machine Timer Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 8 | ueip | | | RW | User External Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 9 | seip | | | RW | Supervisor External Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 10 | vseip | | | RW | VS-level External Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 11 | meip | 0x1 | 0 | RW | Machine External Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| 12 | sgeip | | | RW | HS-level External Interrupt Pending. |
+---------+--------------+----------------+--------+----------+----------------------------------------+
| [31:13] | Reserved_13 | | | Reserved | Reserved |
+---------+--------------+----------------+--------+----------+----------------------------------------+
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+=========+==============+================+=========+=============+========================================+
| 0 | USIP | | 0x0 | WARL | User Software Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 1 | SSIP | | 0x0 | WARL | Supervisor Software Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 2 | VSSIP | | 0x0 | WARL | VS-level Software Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 3 | MSIP | 0x1 | 0x0 | RO_VARIABLE | Machine Software Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 4 | UTIP | | 0x0 | WARL | User Timer Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 5 | STIP | | 0x0 | WARL | Supervisor Timer Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 6 | VSTIP | | 0x0 | WARL | VS-level Timer Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 7 | MTIP | 0x1 | 0x0 | RO_VARIABLE | Machine Timer Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 8 | UEIP | | 0x0 | WARL | User External Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 9 | SEIP | | 0x0 | WARL | Supervisor External Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 10 | VSEIP | | 0x0 | WARL | VS-level External Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 11 | MEIP | 0x1 | 0x0 | RO_VARIABLE | Machine External Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| 12 | SGEIP | | 0x0 | WARL | HS-level External Interrupt Pending. |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
| [31:13] | RESERVED_13 | | 0x0 | WPRI | RESERVED |
+---------+--------------+----------------+---------+-------------+----------------------------------------+
pmpcfg[0-15]
------------
PMPCFG[0-1]
-----------
:Address: 0x3a0-0x3af
:Address: 0x3a0-0x3a1
:Reset Value: 0x00000000
:Privilege Mode: M
:Description: PMP configuration register
+---------+-----------------+----------------+--------+----------+------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+=========+=================+================+========+==========+========================+
| [7:0] | pmp[i*4 + 0]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
+---------+-----------------+----------------+--------+----------+------------------------+
| [15:8] | pmp[i*4 + 1]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
+---------+-----------------+----------------+--------+----------+------------------------+
| [23:16] | pmp[i*4 + 2]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
+---------+-----------------+----------------+--------+----------+------------------------+
| [31:24] | pmp[i*4 + 3]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
+---------+-----------------+----------------+--------+----------+------------------------+
+---------+-----------------+----------------+---------+--------+------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+=========+=================+================+=========+========+========================+
| [7:0] | PMP[I*4 + 0]CFG | [0x00:0xFF] | 0x0 | WARL | pmp configuration bits |
+---------+-----------------+----------------+---------+--------+------------------------+
| [15:8] | PMP[I*4 + 1]CFG | [0x00:0xFF] | 0x0 | WARL | pmp configuration bits |
+---------+-----------------+----------------+---------+--------+------------------------+
| [23:16] | PMP[I*4 + 2]CFG | [0x00:0xFF] | 0x0 | WARL | pmp configuration bits |
+---------+-----------------+----------------+---------+--------+------------------------+
| [31:24] | PMP[I*4 + 3]CFG | [0x00:0xFF] | 0x0 | WARL | pmp configuration bits |
+---------+-----------------+----------------+---------+--------+------------------------+
pmpaddr[0-63]
-------------
PMPADDR[0-7]
------------
:Address: 0x3b0-0x3ef
:Reset Value: 0x00000020
:Address: 0x3b0-0x3b7
:Reset Value: 0x00000000
:Privilege Mode: M
:Description: Physical memory protection address register
+--------+--------------+----------------+------------+----------+---------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+=============================================+
| [31:0] | pmpaddr[i] | 0x00000000 | 0xFFFFFFFF | RW | Physical memory protection address register |
+--------+--------------+----------------+------------+----------+---------------------------------------------+
+--------+--------------+---------------------------+------------+--------+---------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+=============================================+
| [31:0] | PMPADDR[I] | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | Physical memory protection address register |
+--------+--------------+---------------------------+------------+--------+---------------------------------------------+
mcycle
MCYCLE
------
:Address: 0xb00
:Reset Value: 0x0001e253
:Reset Value: 0x00000000
:Privilege Mode: M
:Description: Counts the number of clock cycles executed from an
arbitrary point in time.
+--------+--------------+----------------+------------+----------+-----------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+=============================================================================+
| [31:0] | mcycle | 0x00000000 | 0xFFFFFFFF | RW | Counts the number of clock cycles executed from an arbitrary point in time. |
+--------+--------------+----------------+------------+----------+-----------------------------------------------------------------------------+
+--------+--------------+---------------------------+------------+--------+-----------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+=============================================================================+
| [31:0] | MCYCLE | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | Counts the number of clock cycles executed from an arbitrary point in time. |
+--------+--------------+---------------------------+------------+--------+-----------------------------------------------------------------------------+
minstret
MINSTRET
--------
:Address: 0xb02
@ -410,13 +403,13 @@ minstret
:Description: Counts the number of instructions completed from an
arbitrary point in time.
+--------+--------------+----------------+------------+----------+------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+==============================================================================+
| [31:0] | minstret | 0x00000000 | 0xFFFFFFFF | RW | Counts the number of instructions completed from an arbitrary point in time. |
+--------+--------------+----------------+------------+----------+------------------------------------------------------------------------------+
+--------+--------------+---------------------------+------------+--------+------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+==============================================================================+
| [31:0] | MINSTRET | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | Counts the number of instructions completed from an arbitrary point in time. |
+--------+--------------+---------------------------+------------+--------+------------------------------------------------------------------------------+
mhpmcounter[3-31]
MHPMCOUNTER[3-31]
-----------------
:Address: 0xb03-0xb1f
@ -425,13 +418,13 @@ mhpmcounter[3-31]
:Description: The mhpmcounter is a 64-bit counter. Returns lower 32 bits
in RV32I mode.
+--------+----------------+----------------+------------+----------+---------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+================+================+============+==========+===========================================================================+
| [31:0] | mhpmcounter[i] | 0x00000000 | 0xFFFFFFFF | RW | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
+--------+----------------+----------------+------------+----------+---------------------------------------------------------------------------+
+--------+----------------+---------------------------+------------+--------+---------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+================+===========================+============+========+===========================================================================+
| [31:0] | MHPMCOUNTER[I] | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
+--------+----------------+---------------------------+------------+--------+---------------------------------------------------------------------------+
mcycleh
MCYCLEH
-------
:Address: 0xb80
@ -439,13 +432,13 @@ mcycleh
:Privilege Mode: M
:Description: upper 32 bits of mcycle
+--------+--------------+----------------+------------+----------+-------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+=========================+
| [31:0] | mcycleh | 0x00000000 | 0xFFFFFFFF | RW | upper 32 bits of mcycle |
+--------+--------------+----------------+------------+----------+-------------------------+
+--------+--------------+---------------------------+------------+--------+-------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+=========================+
| [31:0] | MCYCLEH | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | upper 32 bits of mcycle |
+--------+--------------+---------------------------+------------+--------+-------------------------+
minstreth
MINSTRETH
---------
:Address: 0xb82
@ -453,13 +446,13 @@ minstreth
:Privilege Mode: M
:Description: Upper 32 bits of minstret.
+--------+--------------+----------------+------------+----------+----------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+============+==========+============================+
| [31:0] | minstreth | 0x00000000 | 0xFFFFFFFF | RW | Upper 32 bits of minstret. |
+--------+--------------+----------------+------------+----------+----------------------------+
+--------+--------------+---------------------------+------------+--------+----------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+===========================+============+========+============================+
| [31:0] | MINSTRETH | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | Upper 32 bits of minstret. |
+--------+--------------+---------------------------+------------+--------+----------------------------+
mhpmcounter[3-31]h
MHPMCOUNTER[3-31]H
------------------
:Address: 0xb83-0xb9f
@ -468,27 +461,28 @@ mhpmcounter[3-31]h
:Description: The mhpmcounterh returns the upper half word in RV32I
systems.
+--------+-----------------+----------------+------------+----------+----------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+=================+================+============+==========+================================================================+
| [31:0] | mhpmcounter[i]h | 0x00000000 | 0xFFFFFFFF | RW | The mhpmcounterh returns the upper half word in RV32I systems. |
+--------+-----------------+----------------+------------+----------+----------------------------------------------------------------+
+--------+-----------------+---------------------------+------------+--------+----------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+=================+===========================+============+========+================================================================+
| [31:0] | MHPMCOUNTER[I]H | [0x00000000 , 0xFFFFFFFF] | 0x00000000 | WARL | The mhpmcounterh returns the upper half word in RV32I systems. |
+--------+-----------------+---------------------------+------------+--------+----------------------------------------------------------------+
mvendorid
MVENDORID
---------
:Address: 0xf11
:Reset Value: 0x00000602
:Privilege Mode: M
:Description:
:Description: 32-bit read-only register providing the JEDEC manufacturer
ID of the provider of the core.
+--------+--------------+----------------+--------+----------+---------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+========+==========+===============+
| [31:0] | mvendorid | 0x602 | 0 | RW | |
+--------+--------------+----------------+--------+----------+---------------+
+--------+--------------+----------------+------------+-------------+--------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+================+============+=============+============================================================================================+
| [31:0] | MVENDORID | 0x00000602 | 0x00000602 | RO_CONSTANT | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
+--------+--------------+----------------+------------+-------------+--------------------------------------------------------------------------------------------+
marchid
MARCHID
-------
:Address: 0xf12
@ -497,13 +491,13 @@ marchid
:Description: MXLEN-bit read-only register encoding the base
microarchitecture of the hart.
+--------+--------------+----------------+--------+----------+-------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+========+==========+===============================================================================+
| [31:0] | marchid | 0x3 | 0 | RW | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
+--------+--------------+----------------+--------+----------+-------------------------------------------------------------------------------+
+--------+--------------+----------------+------------+-------------+-------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+================+============+=============+===============================================================================+
| [31:0] | MARCHID | 0x00000003 | 0x00000003 | RO_CONSTANT | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
+--------+--------------+----------------+------------+-------------+-------------------------------------------------------------------------------+
mimpid
MIMPID
------
:Address: 0xf13
@ -512,13 +506,13 @@ mimpid
:Description: Provides a unique encoding of the version of the processor
implementation.
+--------+--------------+----------------+--------+----------+----------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+========+==========+============================================================================+
| [31:0] | mimpid | 0x0 | 0 | RW | Provides a unique encoding of the version of the processor implementation. |
+--------+--------------+----------------+--------+----------+----------------------------------------------------------------------------+
+--------+--------------+----------------+------------+-------------+----------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+================+============+=============+============================================================================+
| [31:0] | MIMPID | 0x00000000 | 0x00000000 | RO_CONSTANT | Provides a unique encoding of the version of the processor implementation. |
+--------+--------------+----------------+------------+-------------+----------------------------------------------------------------------------+
mhartid
MHARTID
-------
:Address: 0xf14
@ -527,9 +521,9 @@ mhartid
:Description: MXLEN-bit read-only register containing the integer ID of
the hardware thread running the code.
+--------+--------------+----------------+--------+----------+-------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Mask | Access | Description |
+========+==============+================+========+==========+=================================================================================================+
| [31:0] | mhartid | 0x0 | 0 | RW | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
+--------+--------------+----------------+--------+----------+-------------------------------------------------------------------------------------------------+
+--------+--------------+----------------+------------+-------------+-------------------------------------------------------------------------------------------------+
| Bits | Field Name | Legal Values | Reset | Type | Description |
+========+==============+================+============+=============+=================================================================================================+
| [31:0] | MHARTID | 0x00000000 | 0x00000000 | RO_CONSTANT | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
+--------+--------------+----------------+------------+-------------+-------------------------------------------------------------------------------------------------+

60
config/gen_from_riscv_config/cv32a65x/isa/isa.md
View file

@ -18,17 +18,17 @@ Author: Abdessamii Oukalrazqou
|Zicsr|[RV32Zicsr Control and Status Register Instructions](#RV32Zicsr Control and Status Register Instructions)|All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. |
|Zifencei|[RVZifencei Instruction Fetch Fence](#RVZifencei Instruction Fetch Fence)|FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart. Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to it instruction fetches. |
|Zba|[RVZba Address generation instructions](#RVZba Address generation instructions)|The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw added in this extension can be used when the index is to be interpreted as an unsigned word. |
|Zbb|[RVZbb Basic bit-manipulation](#RVZbb Basic bit-manipulation)|The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name. |
|Zbc|[RVZbc Carry-less multiplication](#RVZbc Carry-less multiplication)|Carry-less multiplication is the multiplication in the polynomial ring over GF(2). clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product. clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product. |
|Zbs|[RVZbs Single bit Instructions](#RVZbs Single bit Instructions)|The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. |
|Zicond|[RV32Zicond Integer Conditional Instructions](#RV32Zicond Integer Conditional Instructions)|The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand). Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions |
|Zcb|[RV32Zcb Code Size Reduction Instructions](#RV32Zcb Code Size Reduction Instructions)|Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions. |
|Zicntr|[Zicntr](#Zicntr)|No info found yet for extension Zicntr|
|Zbb|[Zbb](#Zbb)|No info found yet for extension Zbb|
|Zbc|[Zbc](#Zbc)|No info found yet for extension Zbc|
### RV32I Base Integer Instructions
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|ADDI |[addi](#addi)|x[rd] = x[rs1] + sext(imm[11:0])|NONE|NONE |add sign-extended 12-bit immediate to register rs1, and store the result in register rd.|Integer_Register_Immediate_Operations|
|ADDI |[addi rd, rs1, imm[11:0]](#addi rd, rs1, imm[11:0])|x[rd] = x[rs1] + sext(imm[11:0])|NONE|NONE |add sign-extended 12-bit immediate to register rs1, and store the result in register rd.|Integer_Register_Immediate_Operations|
|ANDI |[andi rd, rs1, imm[11:0]](#andi rd, rs1, imm[11:0])|x[rd] = x[rs1] & sext(imm[11:0])|NONE|NONE |perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd.|Integer_Register_Immediate_Operations|
|ORI |[ori rd, rs1, imm[11:0]](#ori rd, rs1, imm[11:0])|x[rd] = x[rs1] \| sext(imm[11:0])|NONE|NONE |perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.|Integer_Register_Immediate_Operations|
|XORI |[xori rd, rs1, imm[11:0]](#xori rd, rs1, imm[11:0])|x[rd] = x[rs1] ^ sext(imm[11:0])|NONE|NONE |perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.|Integer_Register_Immediate_Operations|
@ -143,6 +143,43 @@ Author: Abdessamii Oukalrazqou
|SH3ADD.UW |[sh3add.uw rd, rs1, rs2](#sh3add.uw rd, rs1, rs2)|X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 3)|NONE|NONE |This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 3 places. |Address generation instructions|
|SLLI.UW |[slli.uw rd, rs1, imm](#slli.uw rd, rs1, imm)|X(rd) = (EXTZ(X(rs)[31..0]) << imm)|NONE|NONE |This instruction takes the least-significant word of rs1, zero-extends it, and shifts it left by the immediate. |Address generation instructions|
### RVZbb Basic bit-manipulation
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|ANDN |[andn rd, rs1, rs2](#andn rd, rs1, rs2)|X(rd) = X(rs1) & ~X(rs2)|NONE|NONE |Performs bitwise AND operation between rs1 and bitwise inversion of rs2.|Logical_with_negate|
|ORN |[orn rd, rs1, rs2](#orn rd, rs1, rs2)|X(rd) = X(rs1) \| ~X(rs2)|NONE|NONE |Performs bitwise OR operation between rs1 and bitwise inversion of rs2.|Logical_with_negate|
|XNOR |[xnor rd, rs1, rs2](#xnor rd, rs1, rs2)|X(rd) = ~(X(rs1) ^ X(rs2))|NONE|NONE |Performs bitwise XOR operation between rs1 and rs2, then complements the result.|Logical_with_negate|
|CLZ |[clz rd, rs](#clz rd, rs)|if [x[i]] == 1 then return(i) else return -1|NONE|NONE |Counts leading zero bits in rs.|Count_leading_trailing_zero_bits|
|CTZ |[ctz rd, rs](#ctz rd, rs)|if [x[i]] == 1 then return(i) else return xlen;|NONE|NONE |Counts trailing zero bits in rs.|Count_leading_trailing_zero_bits|
|CLZW |[clzw rd, rs](#clzw rd, rs)|if [x[i]] == 1 then return(i) else return -1|NONE|NONE |Counts leading zero bits in the least-significant word of rs.|Count_leading_trailing_zero_bits|
|CTZW |[ctzw rd, rs](#ctzw rd, rs)|if [x[i]] == 1 then return(i) else return 32;|NONE|NONE |Counts trailing zero bits in the least-significant word of rs.|Count_leading_trailing_zero_bits|
|CPOP |[cpop rd, rs](#cpop rd, rs)|if rs[i] == 1 then bitcount = bitcount + 1 else ()|NONE|NONE |Counts set bits in rs.|Count_population|
|CPOPW |[cpopw rd, rs](#cpopw rd, rs)|if rs[i] == 0b1 then bitcount = bitcount + 1 else ()|NONE|NONE |Counts set bits in the least-significant word of rs.|Count_population|
|MAX |[max rd, rs1, rs2](#max rd, rs1, rs2)|if rs1_val <_s rs2_val then rs2_val else rs1_val|NONE|NONE |Returns the larger of two signed integers.|Integer_minimum_maximum|
|MAXU |[maxu rd, rs1, rs2](#maxu rd, rs1, rs2)|if rs1_val <_u rs2_val then rs2_val else rs1_val|NONE|NONE |Returns the larger of two unsigned integers.|Integer_minimum_maximum|
|MIN |[min rd, rs1, rs2](#min rd, rs1, rs2)|if rs1_val <_s rs2_val then rs1_val else rs2_val|NONE|NONE |Returns the smaller of two signed integers.|Integer_minimum_maximum|
|MINU |[minu rd, rs1, rs2](#minu rd, rs1, rs2)|if rs1_val <_u rs2_val then rs1_val else rs2_val|NONE|NONE |Returns the smaller of two unsigned integers.|Integer_minimum_maximum|
|SEXT.B |[sext.b rd, rs](#sext.b rd, rs)|X(rd) = EXTS(X(rs)[7..0])|NONE|NONE |Sign-extends the least-significant byte in the source to XLEN.|Sign_and_zero_extension|
|SEXT.H |[sext.h rd, rs](#sext.h rd, rs)|X(rd) = EXTS(X(rs)[15..0])|NONE|NONE |Sign-extends the least-significant halfword in rs to XLEN.|Sign_and_zero_extension|
|ZEXT.H |[zext.h rd, rs](#zext.h rd, rs)|X(rd) = EXTZ(X(rs)[15..0])|NONE|NONE |Zero-extends the least-significant halfword of the source to XLEN.|Sign_and_zero_extension|
|ROL |[rol rd, rs1, rs2](#rol rd, rs1, rs2)|(X(rs1) << log2(XLEN)) \| (X(rs1) >> (xlen - log2(XLEN)))|NONE|NONE |Performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2.|Bitwise_rotation|
|ROR |[ror rd, rs1, rs2](#ror rd, rs1, rs2)|(X(rs1) >> log2(XLEN)) \| (X(rs1) << (xlen - log2(XLEN)))|NONE|NONE |Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.|Bitwise_rotation|
|RORI |[rori rd, rs1, shamt](#rori rd, rs1, shamt)|(X(rs1) >> log2(XLEN)) \| (X(rs1) << (xlen - log2(XLEN)))|NONE|NONE |Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of shamt.|Bitwise_rotation|
|ROLW |[rolw rd, rs1, rs2](#rolw rd, rs1, rs2)|EXTS((rs1 << X(rs2)[4..0]) \| (rs1 >> (32 - X(rs2)[4..0])))|NONE|NONE |Performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.|Bitwise_rotation|
|RORIW |[roriw rd, rs1, shamt](#roriw rd, rs1, shamt)|(rs1_data >> shamt[4..0]) \| (rs1_data << (32 - shamt[4..0]))|NONE|NONE |Performs a rotate right on the least-significant word of rs1 by the amount in least-significant log2(XLEN) bits of shamt.|Bitwise_rotation|
|RORW |[rorw rd, rs1, rs2](#rorw rd, rs1, rs2)|(rs1 >> X(rs2)[4..0]) \| (rs1 << (32 - X(rs2)[4..0]))|NONE|NONE |Performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.|Bitwise_rotation|
|ORC.b |[orc.b rd, rs](#orc.b rd, rs)|if { input[(i + 7)..i] == 0 then 0b00000000 else 0b11111111|NONE|NONE |Sets the bits of each byte in rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.|OR_Combine|
|REV8 |[rev8 rd, rs](#rev8 rd, rs)|output[i..(i + 7)] = input[(j - 7)..j]|NONE|NONE |Reverses the order of the bytes in rs.|Byte_reverse|
### RVZbc Carry-less multiplication
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|CLMUL |[clmul rd, rs1, rs2](#clmul rd, rs1, rs2)|foreach (i from 1 to xlen by 1) { output = if ((rs2 >> i) & 1) then output ^ (rs1 << i); else output; } |NONE|NONE |clmul produces the lower half of the 2.XLEN carry-less product. |Carry-less multiplication Operations|
|CLMULH |[clmulh rd, rs1, rs2](#clmulh rd, rs1, rs2)|foreach (i from 1 to xlen by 1) { output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i)) else output } |NONE|NONE |clmulh produces the upper half of the 2.XLEN carry-less product. |Carry-less multiplication Operations|
|CLMULR |[clmulr rd, rs1, rs2](#clmulr rd, rs1, rs2)|foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i - 1)) else output } |NONE|NONE |clmulr produces bits 2.XLEN-2:XLEN-1 of the 2.XLEN carry-less product. |Carry-less multiplication Operations|
### RVZbs Single bit Instructions
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
@ -156,9 +193,18 @@ Author: Abdessamii Oukalrazqou
|BSET |[bset rd, rs1, rs2](#bset rd, rs1, rs2)|X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1)))|NONE|NONE |This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. |Single_bit_Operations|
|BSETI |[bseti rd, rs1, shamt](#bseti rd, rs1, shamt)|X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1)))|NONE|NONE |This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. |Single_bit_Operations|
### RV32Zicond Integer Conditional Instructions
### RV32Zcb Code Size Reduction Instructions
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|CZERO.EQZ |[czero.eqz rd, rs1, rs2](#czero.eqz rd, rs1, rs2)|if (x[rs2] == 0) x[rd] = 0 else x[rs1]|NONE|NONE |This instruction behaves as if there is a conditional branch dependent on rs2 being equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd. |Integer Conditional Operations|
|CZERO.NEZ |[czero.nez rd, rs1, rs2](#czero.nez rd, rs1, rs2)|if (x[rs2] != 0) x[rd] = 0 else x[rs1]|NONE|NONE |This instruction behaves as if there is a conditional branch dependent on rs2 being not equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd. |Integer Conditional Operations|
|C.ZEXT.B |[c.zext.b rd'](#c.zext.b rd')|x[8 + rd'] = zext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. |Code Size Reduction Operations|
|C.SEXT.B |[c.sext.b rd'](#c.sext.b rd')|x[8 + rd'] = sext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations|
|C.ZEXT.H |[c.zext.h rd'](#c.zext.h rd')|x[8 + rd'] = zext(x[8 + rd'][15:0])|NONE|NONE |This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations|
|C.SEXT.H |[c.sext.h rd'](#c.sext.h rd')|x[8 + rd'] = sext(x[8 + rd'][15:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Code Size Reduction Operations|
|C.NOT |[c.not rd'](#c.not rd')|x[8 + rd'] = x[8 + rd'] ^ -1|NONE|NONE |This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. |Code Size Reduction Operations|
|C.MUL |[c.mul rd', rs2'](#c.mul rd', rs2')|x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0]|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. |Code Size Reduction Operations|
|C.LHU |[c.lhu rd', uimm(rs1')](#c.lhu rd', uimm(rs1'))|x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0])|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. |Code Size Reduction Operations|
|C.LH |[c.lh rd', uimm(rs1')](#c.lh rd', uimm(rs1'))|x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0])|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. |Code Size Reduction Operations|
|C.LBU |[c.lbu rd', uimm(rs1')](#c.lbu rd', uimm(rs1'))|x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0])|NONE|NONE |This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. |Code Size Reduction Operations|
|C.SH |[c.sh rs2', uimm(rs1')](#c.sh rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2']|NONE|an exception raised if the memory address isn't aligned (2-byte boundary).|This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. |Code Size Reduction Operations|
|C.SB |[c.sb rs2', uimm(rs1')](#c.sb rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2']|NONE|NONE |This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. |Code Size Reduction Operations|

145
config/gen_from_riscv_config/cv32a65x/isa/isa.rst
View file

@ -37,16 +37,19 @@ Instructions
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zba | RVZba Address generation instructions_ | The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw added in this extension can be used when the index is to be interpreted as an unsigned word. |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zbb | RVZbb Basic bit-manipulation_ | The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. |
| | | While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name. |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zbc | RVZbc Carry-less multiplication_ | Carry-less multiplication is the multiplication in the polynomial ring over GF(2). |
| | | clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product. |
| | | clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product. |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zbs | RVZbs Single bit Instructions_ | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zicond | RV32Zicond Integer Conditional Instructions_ | The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand). Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions |
| Zcb | RV32Zcb Code Size Reduction Instructions_ | Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions. |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zicntr | Zicntr_ | No info found yet for extension Zicntr |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zbb | Zbb_ | No info found yet for extension Zbb |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Zbc | Zbc_ | No info found yet for extension Zbc |
+---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
RV32I Base Integer Instructions
-------------------------------
@ -55,7 +58,7 @@ RV32I Base Integer Instructions
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+========+==========================+===================================================================+==================+================================================================================================================================================================================================================================================================================+=============================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================+==================================================+
| ADDI | addi | x[rd] = x[rs1] + sext(imm[11:0]) | NONE | NONE | add sign-extended 12-bit immediate to register rs1, and store the result in register rd. | Integer_Register_Immediate_Operations |
| ADDI | addi rd, rs1, imm[11:0] | x[rd] = x[rs1] + sext(imm[11:0]) | NONE | NONE | add sign-extended 12-bit immediate to register rs1, and store the result in register rd. | Integer_Register_Immediate_Operations |
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
| ANDI | andi rd, rs1, imm[11:0] | x[rd] = x[rs1] & sext(imm[11:0]) | NONE | NONE | perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations |
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
@ -274,6 +277,82 @@ RVZba Address generation instructions
| SLLI.UW | slli.uw rd, rs1, imm | X(rd) = (EXTZ(X(rs)[31..0]) << imm) | NONE | NONE | This instruction takes the least-significant word of rs1, zero-extends it, and shifts it left by the immediate. | Address generation instructions |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+
RVZbb Basic bit-manipulation
----------------------------
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+========+======================+==============================================================+==================+====================+=====================================================================================================================================================================+==================================+
| ANDN | andn rd, rs1, rs2 | X(rd) = X(rs1) & ~X(rs2) | NONE | NONE | Performs bitwise AND operation between rs1 and bitwise inversion of rs2. | Logical_with_negate |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| ORN | orn rd, rs1, rs2 | X(rd) = X(rs1) | ~X(rs2) | NONE | NONE | Performs bitwise OR operation between rs1 and bitwise inversion of rs2. | Logical_with_negate |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| XNOR | xnor rd, rs1, rs2 | X(rd) = ~(X(rs1) ^ X(rs2)) | NONE | NONE | Performs bitwise XOR operation between rs1 and rs2, then complements the result. | Logical_with_negate |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| CLZ | clz rd, rs | if [x[i]] == 1 then return(i) else return -1 | NONE | NONE | Counts leading zero bits in rs. | Count_leading_trailing_zero_bits |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| CTZ | ctz rd, rs | if [x[i]] == 1 then return(i) else return xlen; | NONE | NONE | Counts trailing zero bits in rs. | Count_leading_trailing_zero_bits |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| CLZW | clzw rd, rs | if [x[i]] == 1 then return(i) else return -1 | NONE | NONE | Counts leading zero bits in the least-significant word of rs. | Count_leading_trailing_zero_bits |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| CTZW | ctzw rd, rs | if [x[i]] == 1 then return(i) else return 32; | NONE | NONE | Counts trailing zero bits in the least-significant word of rs. | Count_leading_trailing_zero_bits |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| CPOP | cpop rd, rs | if rs[i] == 1 then bitcount = bitcount + 1 else () | NONE | NONE | Counts set bits in rs. | Count_population |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| CPOPW | cpopw rd, rs | if rs[i] == 0b1 then bitcount = bitcount + 1 else () | NONE | NONE | Counts set bits in the least-significant word of rs. | Count_population |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| MAX | max rd, rs1, rs2 | if rs1_val <_s rs2_val then rs2_val else rs1_val | NONE | NONE | Returns the larger of two signed integers. | Integer_minimum_maximum |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| MAXU | maxu rd, rs1, rs2 | if rs1_val <_u rs2_val then rs2_val else rs1_val | NONE | NONE | Returns the larger of two unsigned integers. | Integer_minimum_maximum |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| MIN | min rd, rs1, rs2 | if rs1_val <_s rs2_val then rs1_val else rs2_val | NONE | NONE | Returns the smaller of two signed integers. | Integer_minimum_maximum |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| MINU | minu rd, rs1, rs2 | if rs1_val <_u rs2_val then rs1_val else rs2_val | NONE | NONE | Returns the smaller of two unsigned integers. | Integer_minimum_maximum |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| SEXT.B | sext.b rd, rs | X(rd) = EXTS(X(rs)[7..0]) | NONE | NONE | Sign-extends the least-significant byte in the source to XLEN. | Sign_and_zero_extension |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| SEXT.H | sext.h rd, rs | X(rd) = EXTS(X(rs)[15..0]) | NONE | NONE | Sign-extends the least-significant halfword in rs to XLEN. | Sign_and_zero_extension |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| ZEXT.H | zext.h rd, rs | X(rd) = EXTZ(X(rs)[15..0]) | NONE | NONE | Zero-extends the least-significant halfword of the source to XLEN. | Sign_and_zero_extension |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| ROL | rol rd, rs1, rs2 | (X(rs1) << log2(XLEN)) | (X(rs1) >> (xlen - log2(XLEN))) | NONE | NONE | Performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2. | Bitwise_rotation |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| ROR | ror rd, rs1, rs2 | (X(rs1) >> log2(XLEN)) | (X(rs1) << (xlen - log2(XLEN))) | NONE | NONE | Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2. | Bitwise_rotation |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| RORI | rori rd, rs1, shamt | (X(rs1) >> log2(XLEN)) | (X(rs1) << (xlen - log2(XLEN))) | NONE | NONE | Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of shamt. | Bitwise_rotation |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| ROLW | rolw rd, rs1, rs2 | EXTS((rs1 << X(rs2)[4..0]) | (rs1 >> (32 - X(rs2)[4..0]))) | NONE | NONE | Performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. | Bitwise_rotation |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| RORIW | roriw rd, rs1, shamt | (rs1_data >> shamt[4..0]) | (rs1_data << (32 - shamt[4..0])) | NONE | NONE | Performs a rotate right on the least-significant word of rs1 by the amount in least-significant log2(XLEN) bits of shamt. | Bitwise_rotation |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| RORW | rorw rd, rs1, rs2 | (rs1 >> X(rs2)[4..0]) | (rs1 << (32 - X(rs2)[4..0])) | NONE | NONE | Performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. | Bitwise_rotation |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| ORC.b | orc.b rd, rs | if { input[(i + 7)..i] == 0 then 0b00000000 else 0b11111111 | NONE | NONE | Sets the bits of each byte in rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set. | OR_Combine |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
| REV8 | rev8 rd, rs | output[i..(i + 7)] = input[(j - 7)..j] | NONE | NONE | Reverses the order of the bytes in rs. | Byte_reverse |
+--------+----------------------+--------------------------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
RVZbc Carry-less multiplication
-------------------------------
+--------+---------------------+------------------------------------------------------------------------------------------+------------------+--------------------+------------------------------------------------------------------------+--------------------------------------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+========+=====================+==========================================================================================+==================+====================+========================================================================+======================================+
| CLMUL | clmul rd, rs1, rs2 | foreach (i from 1 to xlen by 1) { | NONE | NONE | clmul produces the lower half of the 2.XLEN carry-less product. | Carry-less multiplication Operations |
| | | output = if ((rs2 >> i) & 1) then output ^ (rs1 << i); else output; | | | | |
| | | } | | | | |
+--------+---------------------+------------------------------------------------------------------------------------------+------------------+--------------------+------------------------------------------------------------------------+--------------------------------------+
| CLMULH | clmulh rd, rs1, rs2 | foreach (i from 1 to xlen by 1) { | NONE | NONE | clmulh produces the upper half of the 2.XLEN carry-less product. | Carry-less multiplication Operations |
| | | output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i)) else output | | | | |
| | | } | | | | |
+--------+---------------------+------------------------------------------------------------------------------------------+------------------+--------------------+------------------------------------------------------------------------+--------------------------------------+
| CLMULR | clmulr rd, rs1, rs2 | foreach (i from 0 to (xlen - 1) by 1) { | NONE | NONE | clmulr produces bits 2.XLEN-2:XLEN-1 of the 2.XLEN carry-less product. | Carry-less multiplication Operations |
| | | output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i - 1)) else output | | | | |
| | | } | | | | |
+--------+---------------------+------------------------------------------------------------------------------------------+------------------+--------------------+------------------------------------------------------------------------+--------------------------------------+
RVZbs Single bit Instructions
-----------------------------
@ -298,33 +377,33 @@ RVZbs Single bit Instructions
| BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations |
+--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
RV32Zicond Integer Conditional Instructions
-------------------------------------------
RV32Zcb Code Size Reduction Instructions
----------------------------------------
+-----------+------------------------+----------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+===========+========================+========================================+==================+====================+======================================================================================================================================================================================================================================================+================================+
| CZERO.EQZ | czero.eqz rd, rs1, rs2 | if (x[rs2] == 0) x[rd] = 0 else x[rs1] | NONE | NONE | This instruction behaves as if there is a conditional branch dependent on rs2 being equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd. | Integer Conditional Operations |
+-----------+------------------------+----------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| CZERO.NEZ | czero.nez rd, rs1, rs2 | if (x[rs2] != 0) x[rd] = 0 else x[rs1] | NONE | NONE | This instruction behaves as if there is a conditional branch dependent on rs2 being not equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd. | Integer Conditional Operations |
+-----------+------------------------+----------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+========+==========+==============+==================+====================+===============+===========+
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+========+==========+==============+==================+====================+===============+===========+
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+========+==========+==============+==================+====================+===============+===========+
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+==========+=======================+======================================================+==================+============================================================================+==============================================================================================================================================================================================================================================================================================+================================+
| C.ZEXT.B | c.zext.b rd' | x[8 + rd'] = zext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.SEXT.B | c.sext.b rd' | x[8 + rd'] = sext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.ZEXT.H | c.zext.h rd' | x[8 + rd'] = zext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.SEXT.H | c.sext.h rd' | x[8 + rd'] = sext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.NOT | c.not rd' | x[8 + rd'] = x[8 + rd'] ^ -1 | NONE | NONE | This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.MUL | c.mul rd', rs2' | x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0] | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.LHU | c.lhu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.LH | c.lh rd', uimm(rs1') | x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.LBU | c.lbu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0]) | NONE | NONE | This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.SH | c.sh rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2'] | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+
| C.SB | c.sb rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2'] | NONE | NONE | This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations |
+----------+-----------------------+------------------------------------------------------+------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+

2
config/gen_from_riscv_config/requirements.txt
View file

@ -3,4 +3,4 @@ pyyaml
mdutils
restructuredtext-lint
rstcloth
regex
regex

8
config/gen_from_riscv_config/scripts/libs/csr_updater.py
View file

@ -13,7 +13,8 @@
# limitations under the License.
#
# Original Author: Oukalrazqou Abdessamii
""" Module is used to update csr based on yaml file called csr updater"""
""" Module is used to update csr based on yaml file called csr updater """
import re
import yaml
@ -28,13 +29,14 @@ def csr_recursive_update(original_dict, csr_update):
"""
for key, value in csr_update.items():
if key in original_dict.keys():
print(key)
if isinstance(value, dict):
csr_recursive_update(original_dict[key], value)
elif isinstance(value, bool):
if isinstance(original_dict[key], dict):
for k in original_dict[key]:
print(k)
if isinstance(original_dict[key][k], dict):
for sub_key in original_dict[key][k]:
original_dict[key][k][sub_key] = value
else:
@ -85,7 +87,7 @@ def csr_formatter(srcfile, modifile):
else:
if v.get(exclude_key) == cond:
keys_to_remove.append(k)
remove_keys_recursive(v)
remove_keys_recursive(v)
for k in keys_to_remove:
dictionary.pop(k)

2
config/gen_from_riscv_config/scripts/libs/isa_updater.py
View file

@ -14,7 +14,7 @@
#
# Original Author: Oukalrazqou Abdessamii
""" Module is used to update isa based on yaml file called isa updater"""
""" Module is used to update isa based on yaml file called isa updater """
import re

200
config/gen_from_riscv_config/scripts/libs/utils.py
View file

@ -102,11 +102,19 @@ class Field:
"""field class"""
def __init__(
self, name, bitlegal, bitmask, bitmsb, bitlsb, bitWidth, fieldDesc, fieldaccess
self,
name,
bitlegal,
fieldreset,
bitmsb,
bitlsb,
bitWidth,
fieldDesc,
fieldaccess,
):
self.name = name
self.bitlegal = bitlegal
self.bitmask = bitmask
self.fieldreset = fieldreset
self.bitmsb = bitmsb
self.bitlsb = bitlsb
self.bitWidth = bitWidth
@ -226,7 +234,11 @@ class RstAddressBlock(AddressBlockClass):
for i, _ in enumerate(regNameList):
if regRV32List[i] | regRV64List[i]:
summary_table.append(
[regAddressList[i], str(regNameList[i]), str(regDescrList[i])]
[
regAddressList[i],
str(regNameList[i]).upper(),
str(regDescrList[i]),
]
)
r.table(header=["Address", "Register Name", "Description"], data=summary_table)
@ -234,7 +246,7 @@ class RstAddressBlock(AddressBlockClass):
for reg in registerlist:
if reg.RV32 | reg.RV64:
reg_table = []
r.h2(reg.name)
r.h2(reg.name.upper())
r.newline()
r.field("Address", (reg.address))
if reg.resetValue:
@ -252,15 +264,18 @@ class RstAddressBlock(AddressBlockClass):
bits = f"[{field.bitmsb}:{field.bitlsb}]"
_line = [
bits,
field.name,
field.name.upper(),
field.bitlegal,
field.bitmask,
field.fieldreset,
field.fieldaccess,
]
_line.append(field.fieldDesc)
reg_table.append(_line)
_headers = ["Bits", "Field Name", "Legal Values", "Mask", "Access"]
_headers = ["Bits", "Field Name", "Legal Values", "Reset", "Type"]
_headers.append("Description")
reg_table = sorted(
reg_table, key=lambda x: int(x[0].strip("[]").split(":")[0])
)
# table of the register
r.table(header=_headers, data=reg_table)
return r.data
@ -306,31 +321,31 @@ class InstrstBlock(InstructionBlockClass):
r.table(header=["Subset Name", "Name", "Description"], data=summary_table)
for reg in self.Instructionlist:
reg_table = []
_headers = [
"Name",
"Format",
"Pseudocode",
"Invalid_values",
"Exception_raised",
"Description",
"Op Name",
]
if len(reg.Name) > 0:
_headers = [
"Name",
"Format",
"Pseudocode",
"Invalid_values",
"Exception_raised",
"Description",
"Op Name",
]
r.h2(reg.key)
r.newline()
for fieldIndex in list(range(len(reg.Name))):
_line = [
reg.Name[fieldIndex],
reg.Format[fieldIndex],
reg.pseudocode[fieldIndex],
reg.invalid_values[fieldIndex],
reg.exception_raised[fieldIndex],
reg.Description[fieldIndex],
]
_line.append(reg.OperationName[fieldIndex])
reg_table.append(_line)
for fieldIndex in list(range(len(reg.Name))):
_line = [
reg.Name[fieldIndex],
reg.Format[fieldIndex],
reg.pseudocode[fieldIndex],
reg.invalid_values[fieldIndex],
reg.exception_raised[fieldIndex],
reg.Description[fieldIndex],
]
_line.append(reg.OperationName[fieldIndex])
reg_table.append(_line)
# table of the register
r.table(header=_headers, data=reg_table)
r.table(header=_headers, data=reg_table)
return r.data
@ -416,6 +431,7 @@ class InstmdBlock(InstructionBlockClass):
).replace("\n", " ")
reg_table.append(reg.Description[fieldIndex])
reg_table.append(reg.OperationName[fieldIndex])
self.mdFile.new_table(
columns=len(headers),
rows=len(reg.Description) + 1,
@ -438,6 +454,13 @@ class MdAddressBlock(AddressBlockClass):
self.suffix = ".md"
self.mdFile = MdUtils(file_name="none", title="")
def parse_bits(self, bits):
if ":" in bits:
msb, lsb = map(int, bits.strip("[]").split(":")[0])
else:
msb = lsb = int(bits.strip("[]").split(":")[0])
return msb, lsb
def returnAsString(self):
registerlist = sorted(self.registerList, key=lambda reg: reg.address)
regNameList = [reg.name for reg in registerlist if reg.RV32 | reg.RV64]
@ -465,7 +488,7 @@ class MdAddressBlock(AddressBlockClass):
rows.extend(
[
regAddressList[i],
f"[{regNameList[i]}](#{regNameList[i]})",
f"[{regNameList[i].upper()}](#{regNameList[i].upper()})",
str(regDescrList[i]),
]
)
@ -479,34 +502,45 @@ class MdAddressBlock(AddressBlockClass):
self.mdFile.new_header(level=3, title="Registers Description")
for reg in registerlist:
if reg.RV64 | reg.RV32:
headers = ["Bits", "Field Name", "Legal Values", "Mask", "Access"]
headers.append("Description")
self.returnMdRegDesc(
reg.name, reg.address, reg.resetValue, reg.desc, reg.access
)
reg_table = []
_line = []
for field in reg.field:
if field.bitWidth == 1: # only one bit -> no range needed
bits = f"{field.bitlsb}"
else:
bits = f"[{field.bitmsb}:{field.bitlsb}]"
reg_table.append(bits)
reg_table.append(field.name)
reg_table.append(field.bitlegal)
reg_table.append(field.bitmask)
reg_table.append(field.fieldaccess)
reg_table.append(field.fieldDesc)
reg_table.append(
[
bits,
field.name.upper(),
field.bitlegal,
field.fieldreset,
field.fieldaccess,
field.fieldDesc,
]
)
_headers = ["Bits", "Field Name", "Legal Values", "Reset", "Type"]
_headers.append("Description")
reg_table = sorted(
reg_table, key=lambda x: int(x[0].strip("[]").split(":")[0])
)
reg_table_flattened = [
item for sublist in reg_table for item in sublist
]
self.mdFile.new_table(
columns=len(headers),
rows=len(reg.field) + 1,
text=headers + reg_table,
columns=len(_headers),
rows=len(reg_table) + 1,
text=_headers + reg_table_flattened,
text_align="left",
)
return self.mdFile.file_data_text
def returnMdRegDesc(self, name, address, resetValue, desc, access):
self.mdFile.new_header(level=4, title=name)
self.mdFile.new_header(level=4, title=name.upper())
self.mdFile.new_line("---")
self.mdFile.new_line("**Address** " + str(address))
if resetValue:
@ -553,18 +587,19 @@ class CsrParser:
)
bitmsb = int(registerElem.get("rv32", "")[item].get("msb", ""))
bitlsb = int(registerElem.get("rv32", "")[item].get("lsb", ""))
fieldaccess = (
registerElem.get("rv32", "")[item]
.get("shadow_type", "")
.upper()
fieldreset = hex(
int(resetValue, 16) >> (bitlsb) & ((1 << ((bitWidth))) - 1)
)
fieldaccess = ""
legal = registerElem.get("rv32", "")[item].get("type", None)
if legal is None:
bitlegal = ""
bitmask = ""
fieldaccess = "WARL"
fieldDesc = fieldDesc
else:
warl = re.findall(pattern_warl, str(legal.keys()))
if warl:
fieldaccess = warl[0].upper()
legal_2 = (
registerElem.get("rv32", "")[item]
.get("type", None)
@ -579,22 +614,19 @@ class CsrParser:
pattern, str(legal_2["legal"][0])
)
if matches:
legal_value = matches.group(3)
mask = matches.group(4)
bitmask = mask
legal_value = matches.group(2)
bitlegal = legal_value
elif isinstance(legal_2, list):
pattern = r"\s*((?:0x)?[0-9A-Fa-f]+)\s*(.)\s*((?:0x)?[0-9A-Fa-f]+)\s*"
matches = re.search(pattern, legal_2[0])
if matches:
legal_value = matches.group(1)
mask = matches.group(3)
bitmask = mask
legal_value = (
f"[{matches.group(1)} , {matches.group(3)}]"
)
bitlegal = legal_value
else:
mask = 0
legal_value = hex(legal_2)
bitmask = mask
bitlegal = legal_value
pattern = r"((\D+)\d+(.*))-\d+"
match = re.match(pattern, regName)
@ -608,28 +640,41 @@ class CsrParser:
)
else:
fieldName = item
f = Field(
fieldName,
bitlegal,
fieldreset,
bitmsb,
bitlsb,
bitWidth,
fieldDesc,
fieldaccess,
)
field.append(f)
elif isinstance(item, list):
for item_ in item:
fieldName = f"Reserved_{item_[0]}"
bitlsb = item_[0]
bitmsb = item_[len(item_) - 1]
legal = ""
fieldaccess = "Reserved"
fieldaccess = "WPRI"
bitWidth = int(item_[len(item_) - 1]) - int(item_[0]) + 1
fieldDesc = "Reserved"
fieldDesc = "RESERVED"
bitlegal = legal
bitmask = ""
f = Field(
fieldName,
bitlegal,
bitmask,
bitmsb,
bitlsb,
bitWidth,
fieldDesc,
fieldaccess,
)
field.append(f)
fieldreset = hex(
int(resetValue, 16) >> (bitlsb) & ((1 << ((bitWidth))) - 1)
)
f = Field(
fieldName,
bitlegal,
fieldreset,
bitmsb,
bitlsb,
bitWidth,
fieldDesc,
fieldaccess,
)
field.append(f)
elif len(fieldList) == 0:
pattern = r"(\D+)\[(\d+)\-\d+\](.*)"
match = re.match(pattern, regName)
@ -653,12 +698,15 @@ class CsrParser:
bitmsb = registerElem.get("rv32", None).get("msb", None)
bitlsb = registerElem.get("rv32", None).get("lsb", None)
legal = registerElem.get("rv32", "").get("type", None)
fieldaccess = ""
if legal is None:
bitlegal = ""
bitmask = ""
fieldaccess = "RO"
else:
warl = re.findall(pattern_warl, str(legal.keys()))
if warl:
fieldaccess = warl[0].upper()
legal_2 = (
registerElem.get("rv32", "")
.get("type", None)
@ -671,7 +719,9 @@ class CsrParser:
pattern = r"([\w\[\]:]+\s*\w+\s*)(\[\s*((?:0x)?[0-9A-Fa-f]+)\s*\D+\s*(?:((?:0x)?[0-9A-Fa-f]+))?\s*])"
matches = re.search(pattern, str(legal_2["legal"][0]))
if matches:
legal_value = matches.group(3)
legal_value = (
f"[{matches.group(3)} , {matches.group(4)}]"
)
mask = matches.group(4)
bitmask = mask
bitlegal = legal_value
@ -679,15 +729,17 @@ class CsrParser:
pattern = r"([0-9A-Fa-f]+).*([0-9A-Fa-f]+)"
matches = re.search(pattern, legal_2[0])
if matches:
legal_value = matches.group(1)
legal_value = (
f"[{matches.group(1)} , {matches.group(2)}]"
)
mask = matches.group(2)
bitmask = mask
bitlegal = hex(legal_value)
bitlegal = legal_value
else:
bitmask = 0
bitlegal = hex(legal_2)
fieldaccess = registerElem.get("rv32", "").get("shadow_type", "").upper()
bitlegal = "0x" + hex(legal_2)[2:].zfill(int(size / 4))
fieldDesc = regDesc
fieldreset = "0x" + hex(int(resetValue, 16))[2:].zfill(int(size / 4))
if bitlsb is None:
bitlsb = 0
if bitmsb is None:
@ -698,7 +750,7 @@ class CsrParser:
f = Field(
fieldName,
bitlegal,
bitmask,
fieldreset,
bitmsb,
bitlsb,
bitWidth,

2
config/gen_from_riscv_config/scripts/riscv_config_gen.py
View file

@ -30,7 +30,7 @@ if __name__ == "__main__":
parser = argparse.ArgumentParser(description="ipxact2rst")
parser.add_argument("-s", "--srcFile", help="yaml input file")
parser.add_argument("-d", "--destDir", help="write generated file to dir")
parser.add_argument("-m", "--modif", help="ISA Formatter if existe")
parser.add_argument("-m", "--modif", help="ISA /CSR Formatter if exist")
parser.add_argument("-i", "--temp", help="Full ISA Template")
parser.add_argument("-t", "--target", help="Specifiy Config Name")
args, unknown_args = parser.parse_known_args()

191
config/gen_from_riscv_config/templates/isa_template.yaml
View file

@ -18,7 +18,7 @@ RV32Zcb Code Size Reduction Instructions:
zeros into all of the bits more significant than 7.
Pseudocode: x[8 + rd'] = zext(x[8 + rd'][7:0])
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.SEXT.B:
Format: c.sext.b rd'
Description: >
@ -29,7 +29,7 @@ RV32Zcb Code Size Reduction Instructions:
support.
Pseudocode: x[8 + rd'] = sext(x[8 + rd'][7:0])
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.ZEXT.H:
Format: c.zext.h rd'
Description: >
@ -39,7 +39,7 @@ RV32Zcb Code Size Reduction Instructions:
Bit-Manipulation (Zbb) extension support.
Pseudocode: x[8 + rd'] = zext(x[8 + rd'][15:0])
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.SEXT.H:
Format: c.sext.h rd'
Description: >
@ -50,7 +50,7 @@ RV32Zcb Code Size Reduction Instructions:
support.
Pseudocode: x[8 + rd'] = sext(x[8 + rd'][15:0])
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.NOT:
Format: c.not rd'
Description: >
@ -58,7 +58,7 @@ RV32Zcb Code Size Reduction Instructions:
the result to the same register.
Pseudocode: x[8 + rd'] = x[8 + rd'] ^ -1
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.MUL:
Format: c.mul rd', rs2'
Description: >
@ -67,7 +67,7 @@ RV32Zcb Code Size Reduction Instructions:
numbers). It also requires M extension support.
Pseudocode: x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0]
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.LHU:
Format: c.lhu rd', uimm(rs1')
Description: >
@ -76,7 +76,7 @@ RV32Zcb Code Size Reduction Instructions:
is zero extended and is written to rd'.
Pseudocode: x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0])
Invalid_Values: NONE
Exception raised: an exception raised if the memory address isn't aligned
Exception_Raised: an exception raised if the memory address isn't aligned
(2-byte boundary).
C.LH:
Format: c.lh rd', uimm(rs1')
@ -86,7 +86,7 @@ RV32Zcb Code Size Reduction Instructions:
is sign extended and is written to rd'.
Pseudocode: x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0])
Invalid_Values: NONE
Exception raised: an exception raised if the memory address isn't aligned
Exception_Raised: an exception raised if the memory address isn't aligned
(2-byte boundary).
C.LBU:
Format: c.lbu rd', uimm(rs1')
@ -96,7 +96,7 @@ RV32Zcb Code Size Reduction Instructions:
zero extended and is written to rd'.
Pseudocode: x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0])
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
C.SH:
Format: c.sh rs2', uimm(rs1')
Description: >
@ -105,7 +105,7 @@ RV32Zcb Code Size Reduction Instructions:
uimm.
Pseudocode: M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2']
Invalid_Values: NONE
Exception raised: an exception raised if the memory address isn't aligned
Exception_Raised: an exception raised if the memory address isn't aligned
(2-byte boundary).
C.SB:
Format: c.sb rs2', uimm(rs1')
@ -115,7 +115,7 @@ RV32Zcb Code Size Reduction Instructions:
uimm.
Pseudocode: M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2']
Invalid_Values: NONE
Exception raised: NONE
Exception_Raised: NONE
RV32A Atomic Instructions:
Description: >
The standard atomic instruction extension is denoted by instruction
@ -908,7 +908,11 @@ RVZbs Single bit Instructions:
Invalid_Values: NONE
Exception_Raised: NONE
RVZbc Carry-less multiplication:
Subset_Name: Zicb
Description : |
Carry-less multiplication is the multiplication in the polynomial ring over GF(2).
clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product.
clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product.
Subset_Name: Zbc
Instructions:
Carry-less multiplication Operations:
CLMUL:
@ -1264,3 +1268,166 @@ RV32I Base Integer Instructions:
Pseudocode: x[8 + rd'] = sext(x[8 + rd'][7:0])
Invalid_Values: NONE
Exception_Raised: NONE
RVZbb Basic bit-manipulation:
Description : |
The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction.
While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name.
Subset_Name : Zbb
Instructions :
Logical_with_negate:
ANDN:
Format: andn rd, rs1, rs2
Description: Performs bitwise AND operation between rs1 and bitwise inversion of rs2.
Pseudocode: X(rd) = X(rs1) & ~X(rs2)
Invalid_Values: NONE
Exception_Raised: NONE
ORN:
Format: orn rd, rs1, rs2
Description: Performs bitwise OR operation between rs1 and bitwise inversion of rs2.
Pseudocode: X(rd) = X(rs1) | ~X(rs2)
Invalid_Values: NONE
Exception_Raised: NONE
XNOR:
Format: xnor rd, rs1, rs2
Description: Performs bitwise XOR operation between rs1 and rs2, then complements the result.
Pseudocode: X(rd) = ~(X(rs1) ^ X(rs2))
Invalid_Values: NONE
Exception_Raised: NONE
Count_leading_trailing_zero_bits:
CLZ :
Format: clz rd, rs
Description: Counts leading zero bits in rs.
Pseudocode: if [x[i]] == 1 then return(i) else return -1
Invalid_Values: NONE
Exception_Raised: NONE
CTZ :
Format: ctz rd, rs
Description: Counts trailing zero bits in rs.
Pseudocode: if [x[i]] == 1 then return(i) else return xlen;
Invalid_Values: NONE
Exception_Raised: NONE
CLZW:
Format: clzw rd, rs
Description: Counts leading zero bits in the least-significant word of rs.
Pseudocode: if [x[i]] == 1 then return(i) else return -1
Invalid_Values: NONE
Exception_Raised: NONE
CTZW:
Format: ctzw rd, rs
Description: Counts trailing zero bits in the least-significant word of rs.
Pseudocode: if [x[i]] == 1 then return(i) else return 32;
Invalid_Values: NONE
Exception_Raised: NONE
Count_population:
CPOP:
Format: cpop rd, rs
Description: Counts set bits in rs.
Pseudocode: if rs[i] == 1 then bitcount = bitcount + 1 else ()
Invalid_Values: NONE
Exception_Raised: NONE
CPOPW:
Format: cpopw rd, rs
Description: Counts set bits in the least-significant word of rs.
Pseudocode: if rs[i] == 0b1 then bitcount = bitcount + 1 else ()
Invalid_Values: NONE
Exception_Raised: NONE
Integer_minimum_maximum:
MAX:
Format: max rd, rs1, rs2
Description: Returns the larger of two signed integers.
Pseudocode: if rs1_val <_s rs2_val then rs2_val else rs1_val
Invalid_Values: NONE
Exception_Raised: NONE
MAXU:
Format: maxu rd, rs1, rs2
Description: Returns the larger of two unsigned integers.
Pseudocode: if rs1_val <_u rs2_val then rs2_val else rs1_val
Invalid_Values: NONE
Exception_Raised: NONE
MIN:
Format: min rd, rs1, rs2
Description: Returns the smaller of two signed integers.
Pseudocode: if rs1_val <_s rs2_val then rs1_val else rs2_val
Invalid_Values: NONE
Exception_Raised: NONE
MINU:
Format: minu rd, rs1, rs2
Description: Returns the smaller of two unsigned integers.
Pseudocode: if rs1_val <_u rs2_val then rs1_val else rs2_val
Invalid_Values: NONE
Exception_Raised: NONE
Sign_and_zero_extension:
SEXT.B:
Format: sext.b rd, rs
Description: Sign-extends the least-significant byte in the source to XLEN.
Pseudocode: X(rd) = EXTS(X(rs)[7..0])
Invalid_Values: NONE
Exception_Raised: NONE
SEXT.H:
Format: sext.h rd, rs
Description: Sign-extends the least-significant halfword in rs to XLEN.
Pseudocode: X(rd) = EXTS(X(rs)[15..0])
Invalid_Values: NONE
Exception_Raised: NONE
ZEXT.H:
Format: zext.h rd, rs
Description: Zero-extends the least-significant halfword of the source to XLEN.
Pseudocode: X(rd) = EXTZ(X(rs)[15..0])
Invalid_Values: NONE
Exception_Raised: NONE
Bitwise_rotation:
ROL:
Format: rol rd, rs1, rs2
Description: Performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2.
Pseudocode: (X(rs1) << log2(XLEN)) | (X(rs1) >> (xlen - log2(XLEN)))
Invalid_Values: NONE
Exception_Raised: NONE
ROR:
Format: ror rd, rs1, rs2
Description: Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.
Pseudocode: (X(rs1) >> log2(XLEN)) | (X(rs1) << (xlen - log2(XLEN)))
Invalid_Values: NONE
Exception_Raised: NONE
RORI:
Format: rori rd, rs1, shamt
Description: Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of shamt.
Pseudocode: (X(rs1) >> log2(XLEN)) | (X(rs1) << (xlen - log2(XLEN)))
Invalid_Values: NONE
Exception_Raised: NONE
ROLW:
Format: rolw rd, rs1, rs2
Description: Performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
Pseudocode: EXTS((rs1 << X(rs2)[4..0]) | (rs1 >> (32 - X(rs2)[4..0])))
Invalid_Values: NONE
Exception_Raised: NONE
RORIW:
Format: roriw rd, rs1, shamt
Description: Performs a rotate right on the least-significant word of rs1 by the amount in least-significant log2(XLEN) bits of shamt.
Pseudocode: (rs1_data >> shamt[4..0]) | (rs1_data << (32 - shamt[4..0]))
Invalid_Values: NONE
Exception_Raised: NONE
RORW:
Format: rorw rd, rs1, rs2
Description: Performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
Pseudocode: (rs1 >> X(rs2)[4..0]) | (rs1 << (32 - X(rs2)[4..0]))
Invalid_Values: NONE
Exception_Raised: NONE
OR_Combine:
ORC.b:
Format: orc.b rd, rs
Description: Sets the bits of each byte in rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.
Pseudocode: if { input[(i + 7)..i] == 0 then 0b00000000 else 0b11111111
Invalid_Values: NONE
Exception_Raised: NONE
Byte_reverse:
REV8:
Format: rev8 rd, rs
Description: Reverses the order of the bytes in rs.
Pseudocode: output[i..(i + 7)] = input[(j - 7)..j]
Invalid_Values: NONE
Exception_Raised: NONE

32
config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml
View file

@ -5,14 +5,24 @@
misa:
reset-val: 123475
mcycle:
reset-val: 123475
mvendorid:
description: ''
misa:
rv32:
mxl:
shadow_type: ''
pmp :
reset-val: 123475
reset-val: 0x40001106
mcountinhibit:
rv32 :
accessible : false
pmpaddr0:
reset-val: 0x0
# Range control
pmpaddr :
range: 8
pmpcfg :
range : 2
# Exclude mode
exclude :
key : priv_mode
cond : S
exclude :
key : priv_mode
cond : U

14
config/gen_from_riscv_config/updaters/cv32a65x/isa_updater.yaml
View file

@ -3,16 +3,14 @@
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# Author: Abdessamii Oukalrazqou
Zicond : True
m0 : True
# Enable and disable extension
Zicond : False
I : True
Zcb : True
Zcmp : False
RV32I Base Integer Instructions:
Instructions :
Integer_Register_Immediate_Operations:
ADDI:
Format: addi
Zbb : False