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Implement mock mul, mulh, mulhu
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1 changed files with 14 additions and 78 deletions
92
src/mult.sv
92
src/mult.sv
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@ -39,6 +39,7 @@ module mult
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// ----------------
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// Mock Multiplier
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// ----------------
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`ifndef SYNTHESIS
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assign mult_valid_o = mult_valid_i;
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assign mult_trans_id_o = trans_id_i;
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assign mult_ready_o = 1'b1;
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@ -55,11 +56,20 @@ module mult
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result_o = mult_result[63:0];
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end
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MULH:;
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MULH: begin
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mult_result = $signed(operand_a_i) * $signed(operand_b_i);
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result_o = mult_result[127:64];
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end
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MULHU:;
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MULHU: begin
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mult_result = operand_a_i * operand_b_i;
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result_o = mult_result[127:64];
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end
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MULHSU:;
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MULHSU: begin
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mult_result = $signed(operand_a_i) * $unsigned(operand_b_i);
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result_o = mult_result[127:64];
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end
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MULW:;
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@ -81,79 +91,5 @@ module mult
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REMUW:;
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endcase
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end
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// // MUL and MULH is a two cycle instructions
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// logic signed [63:0] result_mult;
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// logic signed [63:0] result_multh;
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// enum logic {FIRST_CYCLE, SECOND_CYCLE} multCS, multNS;
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// logic [TRANS_ID_BITS-1:0] mult_trans_q, mult_trans_n;
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// assign mult_trans_id_o = mult_trans_q;
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// assign result_o = is_low_part_i ? result_mult : result_multh;
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// mult_datapath
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// mult_dp
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// (
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// .operand_a_i (operand_a_i ),
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// .operand_b_i (operand_b_i ),
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// .sign_a_i (sign_a_i ),
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// .sign_b_i (sign_b_i ),
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// .result_low_o (result_mult ),
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// .result_high_o (result_multh )
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// );
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// always_comb begin
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// mult_valid_o = 1'b0;
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// mult_ready_o = 1'b0;
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// multNS = multCS;
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// mult_trans_n = mult_trans_q;
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// unique case (multCS)
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// FIRST_CYCLE: begin
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// mult_valid_o = 1'b0;
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// mult_ready_o = 1'b0;
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// multNS = mult_valid_i ? SECOND_CYCLE : multCS;
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// end
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// SECOND_CYCLE: begin
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// multNS = FIRST_CYCLE;
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// mult_valid_o = 1'b1;
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// mult_ready_o = 1'b1;
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// end
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// default:;
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// endcase
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// end
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// always_ff @(posedge clk_i or negedge rst_ni) begin
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// if(~rst_ni) begin
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// multCS <= FIRST_CYCLE;
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// end else begin
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// multCS <= multNS;
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// mult_trans_n <= mult_trans_q;
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// end
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// end
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// Check if we need sign extension
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`endif
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endmodule
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// module mult_datapath
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// (
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// input logic [63:0] operand_a_i,
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// input logic [63:0] operand_b_i,
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// input logic sign_a_i,
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// input logic sign_b_i,
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// output logic [63:0] result_low_o,
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// output logic [63:0] result_high_o
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// );
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// logic signed [129:0] mult_result;
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// logic signed [64:0] operand_a_ext;
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// logic signed [64:0] operand_b_ext;
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// assign operand_a_ext = $signed({sign_a_i & operand_a_i[63], operand_a_i});
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// assign operand_b_ext = $signed({sign_b_i & operand_b_i[63], operand_b_i});
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// assign mult_result = operand_a_ext * operand_b_ext;
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// assign result_low_o = $signed(mult_result[ 63: 0]);
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// assign result_high_o = $signed(mult_result[127:64]);
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// endmodule
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