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openpiton: Fix simulation issues (#677)

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Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
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tianrui-wei 2021-06-07 18:23:22 +08:00 • committed by GitHub
parent 485662f0c9
commit f9b6f7fbc2
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2 changed files with 5 additions and 1 deletions
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2
Flist.ariane
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@ -77,6 +77,8 @@ src/axi_mem_if/src/axi2mem.sv
src/tech_cells_generic/src/pulp_clock_gating.sv
src/tech_cells_generic/src/cluster_clock_inverter.sv
src/tech_cells_generic/src/pulp_clock_mux2.sv
src/pmp/src/pmp.sv
src/pmp/src/pmp_entry.sv
src/axi_adapter.sv
src/alu.sv
src/fpu_wrap.sv

4
openpiton/ariane_verilog_wrap.sv
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@ -13,7 +13,9 @@
// Description: Ariane Top-level wrapper to break out SV structs to logic vectors.
module ariane_verilog_wrap #(
module ariane_verilog_wrap
import ariane_pkg::*;
#(
parameter int unsigned RASDepth = 2,
parameter int unsigned BTBEntries = 32,
parameter int unsigned BHTEntries = 128,