2 commits

Author	SHA1	Message	Date
Guillaume Chauvon	eb9881efbb	cvxif_fu.sv: add register to hold illegal instruction information (#939) ... It avoids that result from cvxif and illegal instruction use wb bus at the same time	2022-08-16 09:27:32 +02:00
Gchauvon	e197b445fc	Add cv-x-interface (#780) ... * Add top hierarchy modification and rs3 for general purpose register file * CVA6 core modifications to enable CoreV-eXtension-Interface feature * Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6 * CoreV-eXtension-Interface available for FPGA * Add work directories to gitignore * Flist: fix cvxif files * CVXIF: Modification and bugfix for cvxif feature * CVXIF: simplify destination register feature * Make 3rd read port on regfile configurable * example_copro: use fifo_v3 instead of stream_fifo * Makefile: compilation copro using defines * ariane_pkg,riscv_pkg: add parameter to en/disable cvxif * cva6.sv, ariane.sv: add hierarchy between ariane and cva6 * Clean Up code and typo * CVXIF: moved combinatorial part to cvxif_fu module in ex_stage * instr_decoder: rename instr predecoder and package * Clean Up code and typo * cvxif modification to follow style guideline * issue_read_operands.sv: fix always_ff block for cvxif functionnal uni	2021-12-22 12:31:56 +01:00