mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-25 06:37:14 -04:00
8e5872c03b
Since last riscv-isa-manual update (CVA6 commit 67a6ae966):
- minor documentation changes
- new unsupported Zsmctr extension
- add missing asciidoctor-lists gem in dependencies/Gemfile
Gemfile update is needed for ReadTheDocs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
296 lines
11 KiB
Python
Executable file
296 lines
11 KiB
Python
Executable file
# Copyright 2024 Thales DIS France SAS
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#
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# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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#!/usr/bin/python3
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import re
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import sys
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import os
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from classes import Parameter
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from classes import PortIO
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from define_blacklist import define_blacklist
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from parameters_extractor import parameters_extractor
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from parameters_extractor import writeout_parameter_table
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from parameters_extractor import writeout_parameter_table_adoc
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HEADER_RST = """\
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..
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Copyright 2024 Thales DIS France SAS
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Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
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you may not use this file except in compliance with the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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You may obtain a copy of the License at https://solderpad.org/licenses/
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Original Author: Jean-Roch COULON - Thales
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"""
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HEADER_ADOC = """\
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////
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Copyright 2024 Thales DIS France SAS
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Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
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you may not use this file except in compliance with the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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You may obtain a copy of the License at https://solderpad.org/licenses/
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Original Author: Jean-Roch COULON - Thales
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////
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"""
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DEFAULT_PARAMS = {
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'RVE': False,
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'RVQ': False,
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'RVZabha': False,
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'RVZacas': False,
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'RVZawrs': False,
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'RVZfa': False,
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'RVZfbf-RZvfbf': False,
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'RVZfh': False,
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'RVZfinx': False,
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'RVZicbo': False,
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'RVZicfilp': False,
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'RVZpm': False,
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'RVZsmctr': False,
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'RVZsmepmp': False,
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'RVZsmmpm': False,
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'RVZsmrnmi': False,
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'RVZsmstateen': False,
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'RVZsscofpmf': False,
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'RVZssdbltrp': False,
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'RVZsstc': False,
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'RVZtso': False,
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'RVZvk': False,
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'SV': 'SV0'
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}
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def print_to_rst(pathout, target, module, ports, comments):
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fileout = f"{pathout}/port_{module}.rst"
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print("Output file " + fileout)
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with open(fileout, "w", encoding="utf-8") as fout:
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fout.write(HEADER_RST)
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fout.write(f".. _CVA6_{module}_ports:\n\n")
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fout.write(f".. list-table:: **{module} module** IO ports\n")
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fout.write(" :header-rows: 1\n")
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fout.write("\n")
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fout.write(" * - Signal\n")
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fout.write(" - IO\n")
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fout.write(" - Description\n")
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fout.write(" - connexion\n")
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fout.write(" - Type\n")
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for i, port in enumerate(ports):
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fout.write("\n")
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fout.write(f" * - ``{port.name}``\n")
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fout.write(f" - {port.direction}\n")
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fout.write(f" - {port.description}\n")
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fout.write(f" - {port.connexion}\n")
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fout.write(f" - {port.data_type}\n")
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fout.write("\n")
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if len(comments) != 0:
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fout.write(
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f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
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)
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fout.write("\n")
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for comment in comments:
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fout.write(f"| {comment[0]},\n| {comment[1]}\n")
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fout.write("\n")
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def print_to_adoc(pathout, target, module, ports, comments):
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fileout = f"{pathout}/port_{module}.adoc"
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print("Output file " + fileout)
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# format comments
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for comment in comments:
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for i in range(len(comment)):
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comment[i] = comment[i].replace('``', '`')
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comment[i] = comment[i].replace('|', '*')
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with open(fileout, "w", encoding="utf-8") as fout:
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fout.write(HEADER_ADOC)
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fout.write(f"[[_CVA6_{module}_ports]]\n\n")
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fout.write(f".*{module} module* IO ports\n")
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fout.write("|===\n")
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fout.write("|Signal | IO | Description | connexion | Type\n\n")
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for port in ports:
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fout.write(f"|`{port.name}` | {port.direction} | {port.description} | {port.connexion} | {port.data_type}\n\n")
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fout.write("|===\n")
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if len(comments) != 0:
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fout.write(
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f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n\n"
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)
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for comment in comments:
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fout.write(f"{comment[0]},::\n* {comment[1]}\n")
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fout.write("\n")
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def _format_parameter_adoc(name, value):
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if type(value) is bool:
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ret = str(value).lower()
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else:
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ret = str(value)
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return f":{name}: {ret}\n"
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def main():
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import argparse
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parser = argparse.ArgumentParser()
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parser.add_argument("--target", required=True)
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parser.add_argument("--gen-config", help="Generate target variables documentation file")
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parser.add_argument("--gen-parameters", help="Generate target parameters files")
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parser.add_argument("--gen-ports-folder", help="Generate target ports files")
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args = parser.parse_args()
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target = args.target
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parameters = parameters_extractor(target)
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# User_cfg
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export_user_cfg_doc("01_cva6_user/user_cfg_doc.rst", parameters)
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# Parameters
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if args.gen_parameters is not None:
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os.makedirs(os.path.dirname(args.gen_parameters), exist_ok=True)
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writeout_parameter_table_adoc(args.gen_parameters, parameters, target)
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print(f"File {args.gen_parameters} written")
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# Config
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if args.gen_config is not None:
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os.makedirs(os.path.dirname(args.gen_config), exist_ok=True)
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with open(args.gen_config, "w") as fout:
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fout.write(f":ohg-config: {target.upper()}\n")
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for name, value in DEFAULT_PARAMS.items():
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fout.write(_format_parameter_adoc(name, value))
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for name, parameter in parameters.items():
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fout.write(_format_parameter_adoc(name, parameter.value))
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print(f"File {args.gen_config} written")
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# Ports
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if args.gen_ports_folder is not None:
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file = []
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file.append("../core/cva6.sv")
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file.append("../core/frontend/frontend.sv")
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file.append("../core/frontend/bht.sv")
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file.append("../core/frontend/btb.sv")
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file.append("../core/frontend/ras.sv")
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file.append("../core/frontend/instr_queue.sv")
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file.append("../core/frontend/instr_scan.sv")
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file.append("../core/instr_realign.sv")
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file.append("../core/id_stage.sv")
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file.append("../core/issue_stage.sv")
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file.append("../core/ex_stage.sv")
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file.append("../core/commit_stage.sv")
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file.append("../core/controller.sv")
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file.append("../core/csr_regfile.sv")
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file.append("../core/decoder.sv")
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file.append("../core/compressed_decoder.sv")
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file.append("../core/scoreboard.sv")
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file.append("../core/issue_read_operands.sv")
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file.append("../core/alu.sv")
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file.append("../core/branch_unit.sv")
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file.append("../core/csr_buffer.sv")
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file.append("../core/mult.sv")
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file.append("../core/multiplier.sv")
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file.append("../core/serdiv.sv")
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file.append("../core/load_store_unit.sv")
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file.append("../core/load_unit.sv")
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file.append("../core/store_unit.sv")
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file.append("../core/lsu_bypass.sv")
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file.append("../core/cvxif_fu.sv")
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file.append("../core/cache_subsystem/cva6_hpdcache_subsystem.sv")
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black_list = define_blacklist(parameters)
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for filein in file:
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comments = []
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a = re.match(r".*\/(.*).sv", filein)
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module = a.group(1)
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print("Input file " + filein)
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ports = []
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with open(filein, "r", encoding="utf-8") as fin:
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description = "none"
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connexion = "none"
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for line in fin:
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e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line)
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d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
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if d:
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description = d.group(1)
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connexion = d.group(2)
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if e:
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name = e.group(3)
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name = name.replace(",", "")
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data_type = e.group(2)
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data_type = data_type.replace(" ", "")
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if connexion in black_list:
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for i, comment in enumerate(comments):
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if black_list[connexion][0] == comment[0]:
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comment[1] = (
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comment[1]
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+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}"
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)
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break
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else:
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comments.append(
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[
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black_list[connexion][0],
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f"``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}",
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]
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)
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else:
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if name in black_list:
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for i, comment in enumerate(comments):
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if black_list[name][0] == comment[0]:
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comment[1] = (
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comment[1]
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+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[name][1]}"
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)
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break
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else:
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comments.append(
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[
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black_list[name][0],
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f"``{name}`` {e.group(1)}put is tied to {black_list[name][1]}",
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]
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)
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else:
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ports.append(
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PortIO(
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name, e.group(1), data_type, description, connexion
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)
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)
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description = "none"
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connexion = "none"
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print_to_adoc(args.gen_ports_folder, target, module, ports, comments)
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def export_user_cfg_doc(out_path, params):
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with open(out_path, "w", encoding="utf-8") as f:
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f.write(HEADER_RST)
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f.write("""\
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.. _cva6_user_cfg_doc:
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.. list-table:: ``cva6_user_cfg_t`` parameters
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:header-rows: 1
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* - Name
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- Type
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- Description
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""")
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for name, param in params.items():
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f.write("\n")
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f.write(f" * - ``{name}``\n")
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f.write(f" - ``{param.datatype.strip()}``\n")
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f.write(f" - {param.description}\n")
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if __name__ == "__main__":
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main()
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