mirror of
https://github.com/openhwgroup/cva6.git
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c2794df8e6
This MR implements the non-RTL part of CVA6 project changes needed for #2734: * changes to scripts * changes to configuration files * turn off Zifencei support in RTL configuration.
77 lines
2 KiB
Bash
77 lines
2 KiB
Bash
#!/bin/bash
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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# install the required tools
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if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
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source ./verif/regress/install-verilator.sh
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fi
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-tests.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a65x
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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cd verif/sim/
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errors=0
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# 32-bit configurations without MMU
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riscv_tests_list=(
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rv32ui-p-add
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rv32ui-p-lw
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rv32ui-p-sw
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rv32ui-p-beq
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rv32ui-p-jal
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)
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for t in ${riscv_tests_list[@]} ; do
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-${DV_TARGET}-p.yaml --test $t --iss_yaml cva6.yaml --target ${DV_TARGET} --iss=$DV_SIMULATORS $DV_OPTS
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[[ $? > 0 ]] && ((errors++))
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done
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CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common"
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if [[ "$DV_TARGET" != "cv32a65x" ]]; then
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CC_OPTS+=" -nostdlib -lgcc"
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fi
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python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../../config/gen_from_riscv_config/linker/link.ld\
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--gcc_opts="$CC_OPTS" $DV_OPTS
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[[ $? > 0 ]] && ((errors++))
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make -C ../.. clean
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make clean_all
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[[ $errors > 0 ]] && exit 1 ;
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exit 0 ;
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