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https://github.com/openhwgroup/cva6.git
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c2794df8e6
This MR implements the non-RTL part of CVA6 project changes needed for #2734: * changes to scripts * changes to configuration files * turn off Zifencei support in RTL configuration.
75 lines
1.9 KiB
Bash
75 lines
1.9 KiB
Bash
# Copyright 2022 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr)
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-uvm
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fi
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# install the required tools
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if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
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source ./verif/regress/install-verilator.sh
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fi
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source ./verif/regress/install-spike.sh
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source ./verif/sim/setup-env.sh
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if ! [ -n "$DV_HWCONFIG_OPTS" ]; then
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DV_HWCONFIG_OPTS="cv32a65x"
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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make clean
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make -C verif/sim clean_all
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cd verif/sim
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src0=../tests/custom/dhrystone/dhrystone_main.c
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srcA=(
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../tests/custom/dhrystone/dhrystone.c
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../tests/custom/common/syscalls.c
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../tests/custom/common/crt.S
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)
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cflags=(
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-fno-tree-loop-distribute-patterns
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-static
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-mcmodel=medany
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-fvisibility=hidden
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-nostdlib
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-nostartfiles
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-lgcc
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-O3 -fno-inline
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-Wno-implicit-function-declaration
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-Wno-implicit-int
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-I../tests/custom/env
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-I../tests/custom/common
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-I../tests/custom/dhrystone/
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-DNOPRINT
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)
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python3 cva6.py \
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--target hwconfig \
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--hwconfig_opts="$DV_HWCONFIG_OPTS" \
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--iss="$DV_SIMULATORS" \
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--iss_yaml=cva6.yaml \
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--c_tests "$src0" \
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--sv_seed 1 \
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--gcc_opts "${srcA[*]} ${cflags[*]}" \
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--linker ../../config/gen_from_riscv_config/cv32a65x/linker/link.ld \
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$DV_OPTS
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