cva6/pd/synth/scripts
2022-09-01 10:18:13 +02:00
..
dc_setup.tcl Update to synthesis and simulation gate flow (#947) 2022-09-01 10:18:13 +02:00
dc_setup_filenames.tcl Update to synthesis and simulation gate flow (#947) 2022-09-01 10:18:13 +02:00
gate_analysis.py pd: Add Synopsys DC synthesis target (#775) 2021-12-13 19:17:43 +01:00