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b1bdc0c02c
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
27 lines
No EOL
989 B
Tcl
27 lines
No EOL
989 B
Tcl
# Copyright 2018 ETH Zurich and University of Bologna.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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set project ariane
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create_project $project . -force -part $::env(XILINX_PART)
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set_property board_part $::env(XILINX_BOARD) [current_project]
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# set number of threads to 8 (maximum, unfortunately)
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set_param general.maxThreads 8
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set_msg_config -id {[Synth 8-5858]} -new_severity "info"
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set_msg_config -id {[Synth 8-4480]} -limit 1000 |