mirror of
https://github.com/openhwgroup/cva6.git
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70 lines
802 B
Text
70 lines
802 B
Text
*~
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*.nm
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*.elf
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*.hex
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*.itb
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*.map
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*.o
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*.objdump
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*.readelf
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*.gtkw
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*.vcd
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*.vsif
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*.sve
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*.sdb
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test_build
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dsim.env
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dsim.log
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dsim_results
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metrics.db
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metrics_history.db
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xrun_results
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vsim_results
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vmgr_sessions
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__pycache__
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*.swp
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/.cproject
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/.project
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.dvt/
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dvt_build.log
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xrun.history
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xrun.log
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xrun.key
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xcelium.d/
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waves.shm/
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*.log
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stdout.txt
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.vscode
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tests/riscv-compliance/
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tests/riscv-arch-test/
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tests/riscv-tests/
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tests/riscv-isa-sim/
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sim/vcs_results
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sim/verilator_work
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sim/out_*
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sim/Mem_init.txt
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sim/*.txt
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sim/trace*
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sim/simv*
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sim/ucli.key
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sim/.inter*
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sim/.vcs*
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sim/inter*
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sim/novas*
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sim/verdiLog
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sim/Verdi.ses*
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riviera_results/
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*/vendor_lib/dpi_dasm_spike/
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*/vendor_lib/verilab/svlib/
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work*
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vsim.dbg
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*.wlf
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transcript
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.lib-rtl
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.opt-rtl
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tools/spike
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tools/verilator*
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*_results/
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*.signature_output
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ucli.key
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vcs.cmd
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