mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
741e82133d
- Fix the AXI ID width for the CLINT (previously `4`, now `5`) - Parametrise the CLINT's AXI types - Deprecate `axi_[master|slave]_connect` and move to AXI assign macros, as they allow arbitrary AXI types Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
299 lines
14 KiB
Markdown
299 lines
14 KiB
Markdown
# Changelog
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All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
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and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
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## [Unreleased]
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### Added
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### Changed
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- Fix non-setable MEIE bit in MIE CSR
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- Bump `fpnew` to `v0.6.2`
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- Restructured directories to separate CVA6 core from CVA6-APU (FPGA emulation platform for the core). See the [README](README.md#new-directory-structure) for details.
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- Bump `common_cells` to `v1.23.0`
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- Bump `axi` to `v0.31.0`
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- Remove `axi_node` dependency, replace with `axi_xbar` from `axi` repository
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#### Moved Package files
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```
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include/riscv_pkg.sv ==> core/include/riscv_pkg.sv
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src/riscv-dbg/src/dm_pkg.sv ==> corev_apu/riscv-dbg/src/dm_pkg.sv
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include/ariane_pkg.sv ==> core/include/ariane_pkg.sv
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include/std_cache_pkg.sv ==> core/include/std_cache_pkg.sv
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include/wt_cache_pkg.sv ==> core/include/wt_cache_pkg.sv
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src/axi/src/axi_pkg.sv ==> corev_apu/axi/src/axi_pkg.sv
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src/register_interface/src/reg_intf.sv ==> corev_apu/register_interface/src/reg_intf.sv
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src/register_interface/src/reg_intf_pkg.sv ==> corev_apu/register_interface/src/reg_intf_pkg.sv
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include/axi_intf.sv ==> core/include/axi_intf.sv
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tb/ariane_soc_pkg.sv ==> corev_apu/tb/ariane_soc_pkg.sv
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tb/ariane_axi_soc_pkg.sv ==> corev_apu/tb/ariane_axi_soc_pkg.sv
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include/ariane_axi_pkg.sv ==> core/include/ariane_axi_pkg.sv
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src/fpu/src/fpnew_pkg.sv ==> core/fpu/src/fpnew_pkg.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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```
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#### Moved standalone components
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```
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src/frontend/*.sv ==> core/frontend/*.sv
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src/cache_subsystem/*.sv ==> core/cache_subsystem/*.sv (excluding std_no_dcache.sv)
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bootrom/*.sv ==> corev_apu/bootrom/*.sv
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src/clint/*.sv ==> corev_apu/clint/*.sv
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fpga/src/axi2apb/src/*.sv ==> corev_apu/fpga/src/axi2apb/src/*.sv
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fpga/src/apb_timer/*.sv ==> corev_apu/fpga/src/apb_timer/*.sv
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fpga/src/axi_slice/src/*.sv ==> corev_apu/fpga/src/axi_slice/src/*.sv
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src/axi_node/src/*.sv ==> corev_apu/axi_node/src/*.sv
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src/axi_riscv_atomics/src/*.sv ==> corev_apu/src/axi_riscv_atomics/src/*.sv
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src/axi_mem_if/src/*.sv ==> corev_apu/axi_mem_if/src/*.sv
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src/pmp/src/*.sv ==> core/pmp/src/*.sv
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src/rv_plic/rtl/rv_plic_target.sv ==> corev_apu/rv_plic/rtl/rv_plic_target.sv
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src/rv_plic/rtl/rv_plic_gateway.sv ==> corev_apu/rv_plic/rtl/rv_plic_gateway.sv
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src/rv_plic/rtl/plic_regmap.sv ==> corev_apu/rv_plic/rtl/plic_regmap.sv
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src/rv_plic/rtl/plic_top.sv ==> corev_apu/rv_plic/rtl/plic_top.sv
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src/riscv-dbg/src/dmi_cdc.sv ==> corev_apu/riscv-dbg/src/dmi_cdc.sv
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src/riscv-dbg/src/dmi_jtag.sv ==> corev_apu/riscv-dbg/src/dmi_jtag.sv
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src/riscv-dbg/src/dmi_jtag_tap.sv ==> corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
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src/riscv-dbg/src/dm_csrs.sv ==> corev_apu/riscv-dbg/src/dm_csrs.sv
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src/riscv-dbg/src/dm_mem.sv ==> corev_apu/riscv-dbg/src/dm_mem.sv
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src/riscv-dbg/src/dm_sba.sv ==> corev_apu/riscv-dbg/src/dm_sba.sv
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src/riscv-dbg/src/dm_top.sv ==> corev_apu/riscv-dbg/src/dm_top.sv
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src/riscv-dbg/debug_rom/debug_rom.sv ==> corev_apu/riscv-dbg/debug_rom/debug_rom.sv
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src/register_interface/src/apb_to_reg.sv ==> corev_apu/register_interface/src/apb_to_reg.sv
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src/axi/src/axi_multicut.sv ==> corev_apu/axi/src/axi_multicut.sv
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src/common_cells/src/deprecated/generic_fifo.sv ==> common/submodules/common_cells/src/deprecated/generic_fifo.sv
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src/common_cells/src/deprecated/pulp_sync.sv ==> common/submodules/common_cells/src/deprecated/pulp_sync.sv
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src/common_cells/src/deprecated/find_first_one.sv ==> common/submodules/common_cells/src/deprecated/find_first_one.sv
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src/common_cells/src/rstgen_bypass.sv ==> common/submodules/common_cells/src/rstgen_bypass.sv
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src/common_cells/src/rstgen.sv ==> common/submodules/common_cells/src/rstgen.sv
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src/common_cells/src/stream_mux.sv ==> common/submodules/common_cells/src/stream_mux.sv
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src/common_cells/src/stream_demux.sv ==> common/submodules/common_cells/src/stream_demux.sv
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src/common_cells/src/exp_backoff.sv ==> common/submodules/common_cells/src/exp_backoff.sv
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src/axi/src/axi_cut.sv ==> corev_apu/axi/src/axi_cut.sv
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src/axi/src/axi_join.sv ==> corev_apu/axi/src/axi_join.sv
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src/axi/src/axi_delayer.sv ==> corev_apu/axi/src/axi_delayer.sv
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src/axi/src/axi_to_axi_lite.sv ==> corev_apu/axi/src/axi_to_axi_lite.sv
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src/common_cells/src/unread.sv ==> common/submodules/common_cells/src/unread.sv
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src/common_cells/src/sync.sv ==> common/submodules/common_cells/src/sync.sv
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src/common_cells/src/cdc_2phase.sv ==> common/submodules/common_cells/src/cdc_2phase.sv
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src/common_cells/src/spill_register.sv ==> common/submodules/common_cells/src/spill_register.sv
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src/common_cells/src/sync_wedge.sv ==> common/submodules/common_cells/src/sync_wedge.sv
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src/common_cells/src/edge_detect.sv ==> common/submodules/common_cells/src/edge_detect.sv
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src/common_cells/src/stream_arbiter.sv ==> common/submodules/common_cells/src/stream_arbiter.sv
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src/common_cells/src/stream_arbiter_flushable.sv ==> common/submodules/common_cells/src/stream_arbiter_flushable.sv
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src/common_cells/src/deprecated/fifo_v1.sv ==> common/submodules/common_cells/src/deprecated/fifo_v1.sv
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src/common_cells/src/deprecated/fifo_v2.sv ==> common/submodules/common_cells/src/deprecated/fifo_v2.sv
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src/common_cells/src/fifo_v3.sv ==> common/submodules/common_cells/src/fifo_v3.sv
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src/common_cells/src/rr_arb_tree.sv ==> common/submodules/common_cells/src/rr_arb_tree.sv
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src/common_cells/src/deprecated/rrarbiter.sv ==> common/submodules/common_cells/src/deprecated/rrarbiter.sv
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src/common_cells/src/stream_delay.sv ==> common/submodules/common_cells/src/stream_delay.sv
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src/common_cells/src/lfsr_8bit.sv ==> common/submodules/common_cells/src/lfsr_8bit.sv
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src/common_cells/src/lfsr_16bit.sv ==> common/submodules/common_cells/src/lfsr_16bit.sv
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src/common_cells/src/delta_counter.sv ==> common/submodules/common_cells/src/delta_counter.sv
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src/common_cells/src/counter.sv ==> common/submodules/common_cells/src/counter.sv
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src/common_cells/src/shift_reg.sv ==> common/submodules/common_cells/src/shift_reg.sv
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src/tech_cells_generic/src/pulp_clock_gating.sv ==> corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv
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src/tech_cells_generic/src/cluster_clock_inverter.sv ==> corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv
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src/tech_cells_generic/src/pulp_clock_mux2.sv ==> corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
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tb/ariane_testharness.sv ==> corev_apu/tb/ariane_testharness.sv
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tb/ariane_peripherals.sv ==> corev_apu/tb/ariane_peripherals.sv
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tb/common/uart.sv ==> corev_apu/tb/common/uart.sv
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tb/common/SimDTM.sv ==> corev_apu/tb/common/SimDTM.sv
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tb/common/SimJTAG.sv ==> corev_apu/tb/common/SimJTAG.sv
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```
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#### Removed standalone components
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```
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src/util/axi_master_connect.sv
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src/util/axi_slave_connect.sv
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src/util/axi_master_connect_rev.sv
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src/util/axi_slave_connect_rev.sv
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```
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### 4.2.0 - 2019-06-04
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### Added
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- Check execute PMA on instruction frontend
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- Add support for non-contiguous cacheable regions to the PMA checks
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- Provision exponential backoff for AMO SC in L1 D$ miss handler
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### Changed
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- Several small fixes to get the code running on VCS
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- Fix compressed instruction decoding in tracer
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- Fix privilege bug in performance counters. The counters have always been accessible in user mode.
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- Fix RISC-V PK simulation bug caused due to insufficient time to init the `a0` and `a1` registers via the bootrom
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- Fix bug in `wt_axi_adapter` (only appeared when dcache lines were wider than icache lines)
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- Fix potentially long timing path in `axi_lite_interface`
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- Fix VCS elab warning in `load_store_unit`
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- Replace PLIC with implementation from lowRISC
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- Re-work interrupt and debug subsystem to associate requests during decode. This improves stability on for non-idempotent loads.
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- Bump `fpnew` to `v0.5.5`
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- Bump `axi` to `v0.7.0`
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- Bump `common_cells` to `v1.13.1`
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- Bump `riscv-dbg` to `v0.1`
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- Improve FPU pipelining and timing around scoreboard
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- Reworked the `axilite` to PLIC shim for OpenPiton+Ariane
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- Remove `in` and `out` aliases for AXI interfaces
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- Fix small issues with DC synthesis
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- Fix wrong dirtying of `sd` flag in `mstatus`
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- Synthesis fix for `Vivado 2018.3`
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- Clean-up instruction front-end, small IPC improvement
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- Move to Verilator `4.014`
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### 4.1.2
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- Update FPU headers (license)
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### 4.1.1
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### Changed
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- Hotfix: add missing defines for OpenPiton cache system.
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### 4.1.0
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### Added
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- Official support for floating point unit
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- Added AXI-64bit adapter for write-through cache system
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- Added AXI atomic ops and exclusive access support to write-through cache system
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- Provision `riscv-isa-sim` tandem simulation
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- Support for preloading
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### Changed
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- Rerouted the JTAG from PMOD to second channel of FTDI 2232 chip on Genesys 2 board
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- Increase available RAM size on Genesys II board to 1 GiB
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- Fixed problem which decoded compressed hints as illegal instructions
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- Reduce clock frequency of FPGA to 30 MHz to accomodate FPU
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- Bugfixes in write-through cache system
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- ID width fix in random delayer
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### 4.0.0
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### Added
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- Preliminary support for A-Extension
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- Preliminary FP support
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- Preliminary support for OpenPiton cache system
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- Commit log feature
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- Provisioned `aw_top` signal for close to memory atomics
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- FPGA Support
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- Misc bug-fixes
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- Platform Level Interrupt Controller (PLIC)
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- FPGA Bootrom with capability to boot from SD Card
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### Changed
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- core_id / cluster_id inputs have been merged to hard_id input (interface changes)
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- The three AXI ports have been merged into one (interface changes)
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- [Bugfix] Wrong flagging of memory in machine mode if high bits (63-38) are not equal #136
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### 3.0.0
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### Added
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- Added RISC-V compliant debug (interface changes)
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- Implemented basic re-naming
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### Changed
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- [Bugfix] Cache-refill AXI logic (AXI protocol violation)
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- [Bugfix] `MSTATUS` write-able through `SSTATUS` #65
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- [Bugfix] PTW has protocol violation #61
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- [Bugfix] Race-condition #54
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- Removed timer input. Access to mtime will trap and must be handled by M-mode SW.
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### 2.0.2 - 2018-04-08
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### Changed
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- Bugfix in flush behaviour of cache #34
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- Pumped submodules
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### 2.0.1 - 2018-01-26
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### Added
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- Improved instruction fetch fronten-end
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- Add RAS
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- Add support for Bender hardware management
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### Changed
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- Bugfix in non-detected illegal instruction #12
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- Bugfix in non-detected illegal instruction JALR (funct3 != 0)
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- Bugfix in non-detected illegal instruction FENCE (some bit-checks missing)
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### 2.0.0 - 2018-01-26
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### Added
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- Instruction cache added
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- Support for Verilator
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### Changed
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- CI support for verilator
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- Update documentation
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### 1.0.0 - 2018-01-17
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### Added
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- Non-blocking data cache
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- Two AXI interfaces on top level, one for bypassing and one for actual cache-able regions
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- Performance Counters
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- Hardware multiplication (full M-Extension)
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- Support for inter processor interrupts (IPI)
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### Changed
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- Testbench: EOC component now listening on store interface only
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- Store interfaces has been simplified by removing the `valid` signal, a transaction is now considered finished as soon as the dcache gives the grant signal.
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- EOC and dcache checker has been reworked to get rid of absolute path in UVM testbench
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- Fix problem when bypassing the data cache
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### 0.4.0 - 2017-10-13
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Linux booting on FPGA.
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### Added
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- Support for M Extension (mul, div and reminder) in simulation
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- Preliminary debug support
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- Added support for cache management instructions
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### Changed
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- Various bug fixes (branch-prediction, PTW and TLB problems, interrupt handling)
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- Fixed synthesis issues
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## [0.3.0] - 2017-07-15
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### Added
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- Added support for device tree in Ariane's testbench
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### Changed
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- Bugfixes in compressed decoder (legal shifts where throwing an illegal instruction although they where legal)
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- Increase memory size to 16 MB in-order to simulate a full Linux boot
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- Re-worked timer facilities in the CSR section, moved to a platform RTC
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- Core completed its first full Linux boot
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- Changelog design, adhering to a common [standard](http://keepachangelog.com/en/1.0.0/)
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## [0.2.0] - 2017-06-28
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### Added
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- Virtual memory support according to RISC-V privilege specification 1.11 (WIP)
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- Add support for Torture test framework
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### Changed
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- IPC improvements
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- Timing improvements
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- New fetch interface, smaller and ready for macro-op fusion and dual-issue
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## [0.1.0] - 2017-06-21
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### Added
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- Initial development, getting to a stable point
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