mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
8468544156
* Fix latch and timing loop in debu_req * Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE * Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data * Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode. * Initialize instruction traced shadow regfile to zero at start of simulation Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X Fix printouts of assertions Modify bootrom to prevent assignment of X to output * Make separate CI target for AMO tests * Bump fpga-support version * Add AMO tests list * Fix FPU submodule version * Change core_id + cluster_id into hart_id * Rename gitlab CI tests * Replace all SYNTHESIS macros with pragma translate_off * Update readme, bump common cells, benderize * Fix torture make target * Remove unneeded signal
38 lines
684 B
Text
38 lines
684 B
Text
rv64ua-p-amoadd_d
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rv64ua-p-amoadd_w
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rv64ua-p-amoor_d
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rv64ua-p-amoor_w
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rv64ua-p-amoand_d
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rv64ua-p-amoand_w
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rv64ua-p-amoswap_d
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rv64ua-p-amoswap_w
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rv64ua-p-amoxor_d
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rv64ua-p-amoxor_w
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rv64ua-p-amomax_d
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rv64ua-p-amomaxu_d
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rv64ua-p-amomaxu_w
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rv64ua-p-amomax_w
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rv64ua-p-amomin_d
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rv64ua-p-amomin_w
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rv64ua-p-amominu_d
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rv64ua-p-amominu_w
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rv64ua-p-lrsc
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rv64ua-v-amoadd_d
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rv64ua-v-amoadd_w
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rv64ua-v-amoor_d
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rv64ua-v-amoor_w
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rv64ua-v-amoand_d
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rv64ua-v-amoand_w
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rv64ua-v-amoswap_d
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rv64ua-v-amoswap_w
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rv64ua-v-amoxor_d
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rv64ua-v-amoxor_w
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rv64ua-v-amomax_d
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rv64ua-v-amomaxu_d
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rv64ua-v-amomaxu_w
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rv64ua-v-amomax_w
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rv64ua-v-amomin_d
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rv64ua-v-amomin_w
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rv64ua-v-amominu_d
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rv64ua-v-amominu_w
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rv64ua-v-lrsc
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