mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
3a13ae0333
Pre-load the Verilator memories through a side-band signal. We have sub-classed the dtm_t module to prevent the debugger from pre-loading. This commit also updates the stale bootrom. Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
26 lines
368 B
Text
26 lines
368 B
Text
rv64um-p-div
|
|
rv64um-p-divu
|
|
rv64um-p-divuw
|
|
rv64um-p-divw
|
|
rv64um-p-mul
|
|
rv64um-p-mulh
|
|
rv64um-p-mulhsu
|
|
rv64um-p-mulhu
|
|
rv64um-p-mulw
|
|
rv64um-p-rem
|
|
rv64um-p-remu
|
|
rv64um-p-remuw
|
|
rv64um-p-remw
|
|
rv64um-v-div
|
|
rv64um-v-divu
|
|
rv64um-v-divuw
|
|
rv64um-v-divw
|
|
rv64um-v-mul
|
|
rv64um-v-mulh
|
|
rv64um-v-mulhsu
|
|
rv64um-v-mulhu
|
|
rv64um-v-mulw
|
|
rv64um-v-rem
|
|
rv64um-v-remu
|
|
rv64um-v-remuw
|
|
rv64um-v-remw
|