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46 lines
1.5 KiB
Systemverilog
46 lines
1.5 KiB
Systemverilog
// Copyright 2025 Thales DIS France SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Yannick Casamatta - Thales
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// Date: 22/10/2024
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module hpdcache_sram_1rw
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#(
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parameter int unsigned ADDR_SIZE = 0,
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parameter int unsigned DATA_SIZE = 0,
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parameter int unsigned DEPTH = 2**ADDR_SIZE
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)
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(
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input logic clk,
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input logic rst_n,
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input logic cs,
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input logic we,
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input logic [ADDR_SIZE-1:0] addr,
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input logic [DATA_SIZE-1:0] wdata,
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output logic [DATA_SIZE-1:0] rdata
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);
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SyncSpRam #(
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.ADDR_WIDTH(ADDR_SIZE),
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.DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower
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.DATA_WIDTH(DATA_SIZE),
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.OUT_REGS (0),
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.SIM_INIT (1) // for simulation only, will not be synthesized
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// 0: no init, 1: zero init, 2: random init
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// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
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)SyncSpRam_i(
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.Clk_CI (clk),
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.Rst_RBI (rst_n),
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.CSel_SI (cs),
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.WrEn_SI (we),
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.Addr_DI (addr),
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.WrData_DI(wdata),
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.RdData_DO(rdata)
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);
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endmodule : hpdcache_sram_1rw
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