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f7dd49efa5
Introduction This PR adds support for Zbkb extension in the CVA6 core. It also adds the documentation for this extension. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will be followed by other PRs that will add complete support for the Zkn - NIST Algorithm Suite extension. Implementation Zbkb Extension: Added support for the Zbkb instruction set. It essentially expands the Zbb extension with additional instructions useful in cryptography. These instructions are pack, packh, packw, brev8, unzip and zip. Modifications 1. A new bit ZKN was added. The complete Zkn extension will be added under this bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set. 2. Updated the ALU and decoder to recognize and handle Zbkb instructions. Documentation and Reference The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for the Zbkb instruction was also added. Verification Assembly Tests: The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior. The tests include: pack-01.S packh-01.S packw-01.S brev8-01.S unzip-01.S zip-01.S
405 lines
16 KiB
Systemverilog
405 lines
16 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Matthias Baer <baermatt@student.ethz.ch>
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// Author: Igor Loi <igor.loi@unibo.it>
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// Author: Andreas Traber <atraber@student.ethz.ch>
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// Author: Lukas Mueller <lukasmue@student.ethz.ch>
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// Author: Florian Zaruba <zaruabf@iis.ee.ethz.ch>
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//
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// Date: 19.03.2017
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// Description: Ariane ALU based on RI5CY's ALU
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module alu
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import ariane_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter bit HasBranch = 1'b1,
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parameter type fu_data_t = logic
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) (
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// Subsystem Clock - SUBSYSTEM
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input logic clk_i,
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// Asynchronous reset active low - SUBSYSTEM
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input logic rst_ni,
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// FU data needed to execute instruction - ISSUE_STAGE
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input fu_data_t fu_data_i,
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// ALU result - ISSUE_STAGE
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output logic [CVA6Cfg.XLEN-1:0] result_o,
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// ALU branch compare result - branch_unit
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output logic alu_branch_res_o
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);
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logic [CVA6Cfg.XLEN-1:0] operand_a_rev;
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logic [ 31:0] operand_a_rev32;
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logic [ CVA6Cfg.XLEN:0] operand_b_neg;
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logic [CVA6Cfg.XLEN+1:0] adder_result_ext_o;
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logic less; // handles both signed and unsigned forms
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logic [ 31:0] rolw; // Rotate Left Word
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logic [ 31:0] rorw; // Rotate Right Word
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logic [31:0] orcbw, rev8w;
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logic [ $clog2(CVA6Cfg.XLEN) : 0] cpop; // Count Population
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logic [$clog2(CVA6Cfg.XLEN)-1 : 0] lz_tz_count; // Count Leading Zeros
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logic [ 4:0] lz_tz_wcount; // Count Leading Zeros Word
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logic lz_tz_empty, lz_tz_wempty;
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logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
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logic [CVA6Cfg.XLEN-1:0] brev8_reversed;
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logic [ 31:0] unzip_gen;
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logic [ 31:0] zip_gen;
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// bit reverse operand_a for left shifts and bit counting
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generate
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genvar k;
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for (k = 0; k < CVA6Cfg.XLEN; k++)
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assign operand_a_rev[k] = fu_data_i.operand_a[CVA6Cfg.XLEN-1-k];
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for (k = 0; k < 32; k++) assign operand_a_rev32[k] = fu_data_i.operand_a[31-k];
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endgenerate
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// ------
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// Adder
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// ------
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logic adder_op_b_negate;
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logic adder_z_flag;
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logic [CVA6Cfg.XLEN:0] adder_in_a, adder_in_b;
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logic [CVA6Cfg.XLEN-1:0] adder_result;
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logic [CVA6Cfg.XLEN-1:0] operand_a_bitmanip, bit_indx;
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assign adder_op_b_negate = fu_data_i.operation inside {EQ, NE, SUB, SUBW, ANDN, ORN, XNOR};
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always_comb begin
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operand_a_bitmanip = fu_data_i.operand_a;
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if (CVA6Cfg.RVB) begin
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if (CVA6Cfg.IS_XLEN64) begin
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unique case (fu_data_i.operation)
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SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1;
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SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2;
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SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3;
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CTZW: operand_a_bitmanip = operand_a_rev32;
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ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0];
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1;
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SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2;
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SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3;
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CTZ: operand_a_bitmanip = operand_a_rev;
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default: ;
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endcase
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end
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end
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// prepare operand a
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assign adder_in_a = {operand_a_bitmanip, 1'b1};
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// prepare operand b
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assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {CVA6Cfg.XLEN + 1{adder_op_b_negate}};
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assign adder_in_b = operand_b_neg;
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// actual adder
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assign adder_result_ext_o = adder_in_a + adder_in_b;
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assign adder_result = adder_result_ext_o[CVA6Cfg.XLEN:1];
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assign adder_z_flag = ~|adder_result;
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// get the right branch comparison result
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if (HasBranch) begin
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always_comb begin : branch_resolve
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// set comparison by default
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case (fu_data_i.operation)
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EQ: alu_branch_res_o = adder_z_flag;
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NE: alu_branch_res_o = ~adder_z_flag;
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LTS, LTU: alu_branch_res_o = less;
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GES, GEU: alu_branch_res_o = ~less;
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default: alu_branch_res_o = 1'b1;
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endcase
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end
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end else begin
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assign alu_branch_res_o = 1'b0;
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end
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// ---------
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// Shifts
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// ---------
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// TODO: this can probably optimized significantly
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logic shift_left; // should we shift left
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logic shift_arithmetic;
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logic [CVA6Cfg.XLEN-1:0] shift_amt; // amount of shift, to the right
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logic [CVA6Cfg.XLEN-1:0] shift_op_a; // input of the shifter
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logic [ 31:0] shift_op_a32; // input to the 32 bit shift operation
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logic [CVA6Cfg.XLEN-1:0] shift_result;
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logic [ 31:0] shift_result32;
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logic [ CVA6Cfg.XLEN:0] shift_right_result;
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logic [ 32:0] shift_right_result32;
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logic [CVA6Cfg.XLEN-1:0] shift_left_result;
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logic [ 31:0] shift_left_result32;
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assign shift_amt = fu_data_i.operand_b;
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assign shift_left = (fu_data_i.operation == SLL) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SLLW);
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assign shift_arithmetic = (fu_data_i.operation == SRA) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SRAW);
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// right shifts, we let the synthesizer optimize this
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logic [CVA6Cfg.XLEN:0] shift_op_a_64;
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logic [32:0] shift_op_a_32;
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// choose the bit reversed or the normal input for shift operand a
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assign shift_op_a = shift_left ? operand_a_rev : fu_data_i.operand_a;
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assign shift_op_a32 = shift_left ? operand_a_rev32 : fu_data_i.operand_a[31:0];
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assign shift_op_a_64 = {shift_arithmetic & shift_op_a[CVA6Cfg.XLEN-1], shift_op_a};
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assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a32};
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assign shift_right_result = $unsigned($signed(shift_op_a_64) >>> shift_amt[5:0]);
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assign shift_right_result32 = $unsigned($signed(shift_op_a_32) >>> shift_amt[4:0]);
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// bit reverse the shift_right_result for left shifts
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genvar j;
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generate
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for (j = 0; j < CVA6Cfg.XLEN; j++)
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assign shift_left_result[j] = shift_right_result[CVA6Cfg.XLEN-1-j];
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for (j = 0; j < 32; j++) assign shift_left_result32[j] = shift_right_result32[31-j];
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endgenerate
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assign shift_result = shift_left ? shift_left_result : shift_right_result[CVA6Cfg.XLEN-1:0];
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assign shift_result32 = shift_left ? shift_left_result32 : shift_right_result32[31:0];
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// ------------
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// Comparisons
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// ------------
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always_comb begin
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logic sgn;
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sgn = 1'b0;
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if ((fu_data_i.operation == SLTS) ||
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(fu_data_i.operation == LTS) ||
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(fu_data_i.operation == GES) ||
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(fu_data_i.operation == MAX) ||
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(fu_data_i.operation == MIN))
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sgn = 1'b1;
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less = ($signed({sgn & fu_data_i.operand_a[CVA6Cfg.XLEN-1], fu_data_i.operand_a}) <
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$signed({sgn & fu_data_i.operand_b[CVA6Cfg.XLEN-1], fu_data_i.operand_b}));
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end
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if (CVA6Cfg.RVB) begin : gen_bitmanip
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// Count Population + Count population Word
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popcount #(
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.INPUT_WIDTH(CVA6Cfg.XLEN)
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) i_cpop_count (
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.data_i (operand_a_bitmanip),
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.popcount_o(cpop)
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);
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// Count Leading/Trailing Zeros
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// 64b
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lzc #(
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.WIDTH(CVA6Cfg.XLEN),
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.MODE (1)
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) i_clz_64b (
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.in_i(operand_a_bitmanip),
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.cnt_o(lz_tz_count),
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.empty_o(lz_tz_empty)
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);
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if (CVA6Cfg.IS_XLEN64) begin
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//32b
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lzc #(
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.WIDTH(32),
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.MODE (1)
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) i_clz_32b (
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.in_i(operand_a_bitmanip[31:0]),
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.cnt_o(lz_tz_wcount),
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.empty_o(lz_tz_wempty)
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);
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end
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end
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if (CVA6Cfg.RVB) begin : gen_orcbw_rev8w_results
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assign orcbw = {
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{8{|fu_data_i.operand_a[31:24]}},
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{8{|fu_data_i.operand_a[23:16]}},
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{8{|fu_data_i.operand_a[15:8]}},
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{8{|fu_data_i.operand_a[7:0]}}
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};
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assign rev8w = {
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{fu_data_i.operand_a[7:0]},
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{fu_data_i.operand_a[15:8]},
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{fu_data_i.operand_a[23:16]},
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{fu_data_i.operand_a[31:24]}
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};
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if (CVA6Cfg.IS_XLEN64) begin : gen_64b
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assign orcbw_result = {
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{8{|fu_data_i.operand_a[63:56]}},
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{8{|fu_data_i.operand_a[55:48]}},
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{8{|fu_data_i.operand_a[47:40]}},
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{8{|fu_data_i.operand_a[39:32]}},
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orcbw
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};
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assign rev8w_result = {
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rev8w,
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{fu_data_i.operand_a[39:32]},
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{fu_data_i.operand_a[47:40]},
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{fu_data_i.operand_a[55:48]},
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{fu_data_i.operand_a[63:56]}
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};
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end else begin : gen_32b
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assign orcbw_result = orcbw;
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assign rev8w_result = rev8w;
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end
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end
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// ZKN gen block
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if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_gen_block
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genvar i, m, n;
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// Generate brev8_reversed by reversing bits within each byte
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for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen
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for (m = 0; m < 8; m++) begin : reverse_bits
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// Reversing the order of bits within a single byte
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assign brev8_reversed[(i<<3)+m] = fu_data_i.operand_a[(i<<3)+(7-m)];
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end
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end
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// Generate zip and unzip results
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if (CVA6Cfg.IS_XLEN32) begin
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for (n = 0; n < 16; n++) begin : zip_unzip_gen
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// Assigning lower and upper half of operand into the even and odd positions of result
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assign zip_gen[n<<1] = fu_data_i.operand_a[n];
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assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+16];
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// Assigning even and odd bits of operand into lower and upper halves of result
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assign unzip_gen[n] = fu_data_i.operand_a[n<<1];
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assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1];
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end
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end
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end
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// -----------
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// Result MUX
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// -----------
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always_comb begin
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result_o = '0;
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if (CVA6Cfg.IS_XLEN64) begin
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unique case (fu_data_i.operation)
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// Add word: Ignore the upper bits and sign extend to 64 bit
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ADDW, SUBW: result_o = {{CVA6Cfg.XLEN - 32{adder_result[31]}}, adder_result[31:0]};
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SH1ADDUW, SH2ADDUW, SH3ADDUW: result_o = adder_result;
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// Shifts 32 bit
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SLLW, SRLW, SRAW:
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result_o = {{CVA6Cfg.XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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// Standard Operations
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ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[CVA6Cfg.XLEN:1];
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ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[CVA6Cfg.XLEN:1];
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XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[CVA6Cfg.XLEN:1];
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// Adder Operations
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ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result;
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// Shift Operations
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SLL, SRL, SRA: result_o = (CVA6Cfg.IS_XLEN64) ? shift_result : shift_result32;
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// Comparison Operations
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SLTS, SLTU: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, less};
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default: ; // default case to suppress unique warning
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endcase
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if (CVA6Cfg.RVB) begin
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// Index for Bitwise Rotation
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bit_indx = 1 << (fu_data_i.operand_b & (CVA6Cfg.XLEN - 1));
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if (CVA6Cfg.IS_XLEN64) begin
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// rolw, roriw, rorw
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rolw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0]));
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rorw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0]));
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unique case (fu_data_i.operation)
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CLZW, CTZW:
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result_o = (lz_tz_wempty) ? 32 : {{CVA6Cfg.XLEN - 5{1'b0}}, lz_tz_wcount}; // change
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ROLW: result_o = {{CVA6Cfg.XLEN - 32{rolw[31]}}, rolw};
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RORW, RORIW: result_o = {{CVA6Cfg.XLEN - 32{rorw[31]}}, rorw};
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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// Integer minimum/maximum
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MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a;
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MAXU: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a;
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MIN: result_o = ~less ? fu_data_i.operand_b : fu_data_i.operand_a;
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MINU: result_o = ~less ? fu_data_i.operand_b : fu_data_i.operand_a;
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// Single bit instructions operations
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BCLR, BCLRI: result_o = fu_data_i.operand_a & ~bit_indx;
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BEXT, BEXTI: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, |(fu_data_i.operand_a & bit_indx)};
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BINV, BINVI: result_o = fu_data_i.operand_a ^ bit_indx;
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BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx;
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// Count Leading/Trailing Zeros
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CLZ, CTZ:
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result_o = (lz_tz_empty) ? ({{CVA6Cfg.XLEN - $clog2(CVA6Cfg.XLEN) {1'b0}}, lz_tz_count} + 1)
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: {{CVA6Cfg.XLEN - $clog2(CVA6Cfg.XLEN) {1'b0}}, lz_tz_count};
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// Count population
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CPOP, CPOPW: result_o = {{(CVA6Cfg.XLEN - ($clog2(CVA6Cfg.XLEN) + 1)) {1'b0}}, cpop};
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// Sign and Zero Extend
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SEXTB: result_o = {{CVA6Cfg.XLEN - 8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]};
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SEXTH: result_o = {{CVA6Cfg.XLEN - 16{fu_data_i.operand_a[15]}}, fu_data_i.operand_a[15:0]};
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ZEXTH: result_o = {{CVA6Cfg.XLEN - 16{1'b0}}, fu_data_i.operand_a[15:0]};
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// Bitwise Rotation
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ROL:
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result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0])));
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ROR, RORI:
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result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0])));
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ORCB: result_o = orcbw_result;
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REV8: result_o = rev8w_result;
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default:
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if (fu_data_i.operation == SLLIUW && CVA6Cfg.IS_XLEN64)
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result_o = {{CVA6Cfg.XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned
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endcase
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end
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if (CVA6Cfg.RVZiCond) begin
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unique case (fu_data_i.operation)
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CZERO_EQZ:
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result_o = (|fu_data_i.operand_b) ? fu_data_i.operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1
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CZERO_NEZ:
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result_o = (|fu_data_i.operand_b) ? '0 : fu_data_i.operand_a; // move zero to rd if rs2 is nonzero else rs1
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default: ; // default case to suppress unique warning
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endcase
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|
end
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// ZKN instructions
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if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
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unique case (fu_data_i.operation)
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PACK:
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result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
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PACK_H:
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result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
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BREV8: result_o = brev8_reversed;
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default: ;
|
|
endcase
|
|
if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64)
|
|
result_o = {
|
|
{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
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};
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if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
|
|
if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
|
|
end
|
|
end
|
|
endmodule
|