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cva6/core/cvxif_example
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Guillaume Chauvon 3d2ff00b1c
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Modify MSUB, NMADD, NMSUB behaviour to differs from other instructions. (#2712) 
MSUB = rs1 - rs2 - rs3
NMADD = ~(rs1 + rs2 + rs3)
NMSUB = ~(rs1 - rs2 - rs3)
2025-01-17 14:12:08 +01:00
..
include Modify MSUB, NMADD, NMSUB behaviour to differs from other instructions. (#2712) 2025-01-17 14:12:08 +01:00
compressed_instr_decoder.sv Separate RAW and WAW process to fix CVXIF with Superscalar (#2395) 2024-07-26 14:58:18 +02:00
copro_alu.sv Modify MSUB, NMADD, NMSUB behaviour to differs from other instructions. (#2712) 2025-01-17 14:12:08 +01:00
cvxif_example_coprocessor.sv Fixes and Update CVXIF non regression tests, regression and TB (#2424) 2024-08-01 16:06:24 +02:00
instr_decoder.sv Separate RAW and WAW process to fix CVXIF with Superscalar (#2395) 2024-07-26 14:58:18 +02:00