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987c645bb7
This is the third step for #1451. Many values are moved but not all values are moved yet * move NR_SB_ENTRIES & TRANS_ID_BITS * remove default rvfi_instr_t from spike.sv * fifo_v3: ariane_pkg::FPGA_EN becomes a param * move FPGA_EN * inline wt_cache_pkg::L15_SET_ASSOC * move wt_cache_pkg::L15_WAY_WIDTH * inline wt_cache_pkg::L1I_SET_ASSOC * inline wt_cache_pkg::L1D_SET_ASSOC * move wt_cache_pkg::DCACHE_CL_IDX_WIDTH * move ICACHE_TAG_WIDTH * move DCACHE_TAG_WIDTH * move ICACHE_INDEX_WIDTH * move ICACHE_SET_ASSOC * use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC) * move DCACHE_NUM_WORDS * move DCACHE_INDEX_WIDTH * move DCACHE_OFFSET_WIDTH * move DCACHE_BYTE_OFFSET * move DCACHE_DIRTY_WIDTH * move DCACHE_SET_ASSOC_WIDTH * move DCACHE_SET_ASSOC * move CONFIG_L1I_SIZE * move CONFIG_L1D_SIZE * move DCACHE_LINE_WIDTH * move ICACHE_LINE_WIDTH * move ICACHE_USER_LINE_WIDTH * move DCACHE_USER_LINE_WIDTH * DATA_USER_WIDTH = DCACHE_USER_WIDTH * move DCACHE_USER_WIDTH * move FETCH_USER_WIDTH * move FETCH_USER_EN * move LOG2_INSTR_PER_FETCH * move INSTR_PER_FETCH * move FETCH_WIDTH * transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions * move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure * move SV * move vm_mode_t to config_pkg * move MODE_SV * move VPN2 * move PPNW * move ASIDW * move ModeW * move XLEN_ALIGN_BYTES * move DATA_USER_EN * format: apply verible
60 lines
1.9 KiB
Systemverilog
60 lines
1.9 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>, ETH Zurich
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// Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
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// Date: 15.08.2018
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// ******* WIP *******
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// Description: package for the standard Ariane cache subsystem.
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package std_cache_pkg;
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// localparam DECISION_BIT = 30; // bit on which to decide whether the request is cache-able or not
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typedef struct packed {
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logic [1:0] id; // id for which we handle the miss
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logic valid;
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logic we;
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logic [55:0] addr;
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logic [7:0][7:0] wdata;
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logic [7:0] be;
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} mshr_t;
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typedef struct packed {
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logic valid;
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logic [63:0] addr;
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logic [7:0] be;
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logic [1:0] size;
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logic we;
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logic [63:0] wdata;
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logic bypass;
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} miss_req_t;
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typedef struct packed {
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logic req;
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ariane_pkg::ad_req_t reqtype;
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ariane_pkg::amo_t amo;
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logic [3:0] id;
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logic [63:0] addr;
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logic [63:0] wdata;
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logic we;
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logic [7:0] be;
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logic [1:0] size;
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} bypass_req_t;
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typedef struct packed {
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logic gnt;
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logic valid;
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logic [63:0] rdata;
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} bypass_rsp_t;
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endpackage : std_cache_pkg
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