Côme
987c645bb7
Parametrization step 3 ( #1935 )
...
This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
André Sintzoff
a88385c4ce
verible-verilog-format: update to bypass verible limitations ( #1664 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
2023-12-01 08:30:08 +01:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
JeanRochCoulon
716d21c424
Define AXI as cva6 input parameters ( #1315 )
...
* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
2023-07-24 10:34:30 +02:00
Max Bjurling
622409a7e4
Fix infinite loop in std_cache_pkg::one_hot_to_bin ( #1302 )
...
Use int unsigned for loop variable i to avoid wrapping before loop exit
condition is met.
Resolves bug #1301 (https://github.com/openhwgroup/cva6/issues/1301 )
Co-authored-by: Max Bjurling <max.bjurling@planv.tech>
2023-07-12 11:35:23 +02:00
Fatima Saleem
018dbc4210
Resolved Lint WIDTHTRUNC warnings(1/2) ( #1297 )
2023-07-06 11:41:25 +02:00
Luca Colagrande
75250868eb
wb_dcache: Forward atomic transactions to AXI ( #777 )
...
* wb_dcache: Forward "atomic transactions" to AXI
* Correct bugs
* Forward LR/SC atomics
* Fix CI
* miss_handler: Route AMO port through arbiter
* axi_adapter: Correct LOAD AMOs handling
Accept read data only after (or together) handshake on B channel
* Restore old ID
* Correct atop encodings
* Correct AMOs AXI ID
* Correct wb_dcache testbench
Previously not comparing AMOs at all! Due to amo_exp_resp being 'x
* Realign and sign extend 32b request rdata
* Use axi_pkg definitions for ATOPs encoding
* Remove whitespace
* wb_dcache: Style corrections
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
2022-03-09 16:33:37 +01:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
...
* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
