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using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format with default configuration Note: two files are not correctly handled by verible - core/include/std_cache_pkg.sv - core/cache_subsystem/cva6_hpdcache_if_adapter.sv
55 lines
1.6 KiB
Systemverilog
55 lines
1.6 KiB
Systemverilog
// Copyright 2019 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Moritz Schneider, ETH Zurich
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// Date: 2.10.2019
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// Description: PMP package
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package riscv;
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// --------------------
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// Privilege Spec
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// --------------------
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typedef enum logic [1:0] {
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PRIV_LVL_M = 2'b11,
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PRIV_LVL_S = 2'b01,
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PRIV_LVL_U = 2'b00
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} priv_lvl_t;
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// PMP
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typedef enum logic [1:0] {
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OFF = 2'b00,
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TOR = 2'b01,
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NA4 = 2'b10,
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NAPOT = 2'b11
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} pmp_addr_mode_t;
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// PMP Access Type
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typedef enum logic [2:0] {
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ACCESS_NONE = 3'b000,
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ACCESS_READ = 3'b001,
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ACCESS_WRITE = 3'b010,
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ACCESS_EXEC = 3'b100
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} pmp_access_t;
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typedef struct packed {
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logic x;
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logic w;
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logic r;
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} pmpcfg_access_t;
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// packed struct of a PMP configuration register (8bit)
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typedef struct packed {
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logic locked; // lock this configuration
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logic [1:0] reserved;
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pmp_addr_mode_t addr_mode; // Off, TOR, NA4, NAPOT
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pmpcfg_access_t access_type;
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} pmpcfg_t;
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endpackage
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