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https://github.com/openhwgroup/cva6.git
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da74358206
* remove debug module from devicetree * replace uart compatible string with one that uses the FiFos * regenerate bootrom * regenerate FPGA bootrom Signed-off-by: Noah Huetter <huettern@iis.ee.ethz.ch> Co-authored-by: Noah Huetter <huettern@iis.ee.ethz.ch>
82 lines
2.5 KiB
Text
82 lines
2.5 KiB
Text
/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "eth,ariane-bare-dev";
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model = "eth,ariane-bare";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <32768>; // 32.768 kHz
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CPU0: cpu@0 {
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clock-frequency = <50000000>; // 50 MHz
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "eth, ariane", "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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tlb-split;
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// HLIC - hart local interrupt controller
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x10000000>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "eth,ariane-bare-soc", "simple-bus";
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ranges;
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clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
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reg = <0x0 0x2000000 0x0 0xc0000>;
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reg-names = "control";
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};
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// PLIC needs to be disabeld for tandem verification
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// PLIC0: interrupt-controller@c000000 {
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// #address-cells = <0>;
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// #interrupt-cells = <1>;
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// compatible = "sifive,plic-1.0.0", "riscv,plic0";
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// interrupt-controller;
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// interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
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// reg = <0x0 0xc000000 0x0 0x4000000>;
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// riscv,max-priority = <7>;
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// riscv,ndev = <2>;
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// };
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// Specifying the interrupt controller in the devicetree is not necessary.
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// Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during
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// Linux boot (occured with mainline linux 5.14.0).
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// debug-controller@0 {
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// compatible = "riscv,debug-013";
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// interrupts-extended = <&CPU0_intc 65535>;
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// reg = <0x0 0x0 0x0 0x1000>;
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// reg-names = "control";
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// };
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uart@10000000 {
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compatible = "ns16550a";
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reg = <0x0 0x10000000 0x0 0x1000>;
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clock-frequency = <50000000>;
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current-speed = <115200>;
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// interrupt-parent = <&PLIC0>;
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interrupts = <1>;
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reg-shift = <2>; // regs are spaced on 32 bit boundary
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reg-io-width = <4>; // only 32-bit access are supported
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};
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timer@18000000 {
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compatible = "pulp,apb_timer";
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interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>;
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reg = <0x00000000 0x18000000 0x00000000 0x00001000>;
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// interrupt-parent = <&PLIC0>;
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reg-names = "control";
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};
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};
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};
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