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cva6/corev_apu
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AngelaGonzalezMarino 6e0cf8d730
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Altera fpga update (#2790) 
Update Altera APU design to support linux in both 32 and 64 bits
* Move JTAG UART inside peripherals to properly connect the interruput request to PLIC
* Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version
* Update UART read and write operation in bootrom to allow keyboard interrupt
2025-02-25 22:12:55 +01:00
..
altera Altera fpga update (#2790) 2025-02-25 22:12:55 +01:00
axi_mem_if@b494701501 Add user field between memory and caches (#857) 2022-04-20 12:47:07 +02:00
bootrom Remove DROMAJO (#1204) 2023-04-24 23:05:53 +02:00
clint Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
fpga Altera fpga update (#2790) 2025-02-25 22:12:55 +01:00
openpiton Define AXI as cva6 input parameters (#1315) 2023-07-24 10:34:30 +02:00
register_interface@73de8e51b7 Bump register interface to v0.3.1 (#819) 2022-02-10 14:19:12 +01:00
riscv-dbg@e19d69efe7 riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug (#746) 2021-10-01 17:02:34 +02:00
rv_plic@5b5c5a4c1c Bump register interface to v0.3.1 (#819) 2022-02-10 14:19:12 +01:00
src Add parameter type to define which coprocessor is instantiated on CVXIF (#2772) 2025-02-19 08:52:17 +01:00
tb Update rvfi_tracer and cva6.py (#2684) 2025-01-31 13:10:27 +01:00