mirror of
https://github.com/openhwgroup/cva6.git
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da74358206
* remove debug module from devicetree * replace uart compatible string with one that uses the FiFos * regenerate bootrom * regenerate FPGA bootrom Signed-off-by: Noah Huetter <huettern@iis.ee.ethz.ch> Co-authored-by: Noah Huetter <huettern@iis.ee.ethz.ch>
225 lines
6.9 KiB
Systemverilog
225 lines
6.9 KiB
Systemverilog
/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: $filename.v
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*
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* Description: Auto-generated bootrom
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*/
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// Auto-generated code
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module bootrom (
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input logic clk_i,
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input logic req_i,
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = 186;
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const logic [RomSize-1:0][63:0] mem = {
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64'h00000000_00000068,
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64'h74646977_2d6f692d,
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64'h67657200_74666968,
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64'h732d6765_72007374,
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64'h70757272_65746e69,
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64'h00646565_70732d74,
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64'h6e657272_75630073,
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64'h656d616e_2d676572,
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64'h00646564_6e657478,
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64'h652d7374_70757272,
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64'h65746e69_00736567,
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64'h6e617200_656c646e,
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64'h61687000_72656c6c,
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64'h6f72746e_6f632d74,
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64'h70757272_65746e69,
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64'h00736c6c_65632d74,
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64'h70757272_65746e69,
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64'h23007469_6c70732d,
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64'h626c7400_65707974,
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64'h2d756d6d_00617369,
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64'h2c766373_69720073,
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64'h75746174_73006765,
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64'h72006570_79745f65,
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64'h63697665_64007963,
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64'h6e657571_6572662d,
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64'h6b636f6c_63007963,
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64'h6e657571_6572662d,
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64'h65736162_656d6974,
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64'h006c6564_6f6d0065,
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64'h6c626974_61706d6f,
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64'h6300736c_6c65632d,
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64'h657a6973_2300736c,
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64'h6c65632d_73736572,
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64'h64646123_09000000,
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64'h02000000_02000000,
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64'h02000000_006c6f72,
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64'h746e6f63_cc000000,
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64'h08000000_03000000,
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64'h00100000_00000000,
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64'h00000018_00000000,
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64'h5b000000_10000000,
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64'h03000000_07000000,
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64'h06000000_05000000,
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64'h04000000_e4000000,
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64'h10000000_03000000,
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64'h00007265_6d69745f,
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64'h6270612c_706c7570,
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64'h1b000000_0f000000,
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64'h03000000_00003030,
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64'h30303030_38314072,
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64'h656d6974_01000000,
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64'h02000000_04000000,
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64'hf9000000_04000000,
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64'h03000000_02000000,
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64'hef000000_04000000,
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64'h03000000_01000000,
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64'he4000000_04000000,
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64'h03000000_00c20100,
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64'hd6000000_04000000,
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64'h03000000_80f0fa02,
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64'h3f000000_04000000,
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64'h03000000_00100000,
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64'h00000000_00000010,
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64'h00000000_5b000000,
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64'h10000000_03000000,
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64'h00000000_61303535,
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64'h3631736e_1b000000,
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64'h09000000_03000000,
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64'h00000030_30303030,
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64'h30303140_74726175,
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64'h01000000_02000000,
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64'h006c6f72_746e6f63,
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64'hcc000000_08000000,
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64'h03000000_00000c00,
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64'h00000000_00000002,
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64'h00000000_5b000000,
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64'h10000000_03000000,
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64'h07000000_01000000,
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64'h03000000_01000000,
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64'hb8000000_10000000,
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64'h03000000_00000000,
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64'h30746e69_6c632c76,
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64'h63736972_1b000000,
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64'h0d000000_03000000,
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64'h00000030_30303030,
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64'h30324074_6e696c63,
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64'h01000000_b1000000,
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64'h00000000_03000000,
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64'h00007375_622d656c,
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64'h706d6973_00636f73,
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64'h2d657261_622d656e,
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64'h61697261_2c687465,
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64'h1b000000_1f000000,
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64'h03000000_02000000,
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64'h0f000000_04000000,
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64'h03000000_02000000,
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64'h00000000_04000000,
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64'h03000000_00636f73,
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64'h01000000_02000000,
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64'h00000010_00000000,
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64'h00000080_00000000,
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64'h5b000000_10000000,
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64'h03000000_00007972,
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64'h6f6d656d_4f000000,
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64'h07000000_03000000,
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64'h00303030_30303030,
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64'h38407972_6f6d656d,
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64'h01000000_02000000,
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64'h02000000_02000000,
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64'h01000000_a9000000,
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64'h04000000_03000000,
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64'h00006374_6e692d75,
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64'h70632c76_63736972,
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64'h1b000000_0f000000,
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64'h03000000_94000000,
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64'h00000000_03000000,
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64'h01000000_83000000,
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64'h04000000_03000000,
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64'h00000000_72656c6c,
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64'h6f72746e_6f632d74,
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64'h70757272_65746e69,
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64'h01000000_79000000,
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64'h00000000_03000000,
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64'h00003933_76732c76,
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64'h63736972_70000000,
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64'h0b000000_03000000,
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64'h00006364_66616d69,
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64'h34367672_66000000,
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64'h0b000000_03000000,
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64'h00000076_63736972,
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64'h00656e61_69726120,
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64'h2c687465_1b000000,
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64'h12000000_03000000,
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64'h00000000_79616b6f,
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64'h5f000000_05000000,
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64'h03000000_00000000,
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64'h5b000000_04000000,
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64'h03000000_00757063,
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64'h4f000000_04000000,
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64'h03000000_80f0fa02,
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64'h3f000000_04000000,
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64'h03000000_00000030,
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64'h40757063_01000000,
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64'h00800000_2c000000,
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64'h04000000_03000000,
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64'h00000000_0f000000,
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64'h04000000_03000000,
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64'h01000000_00000000,
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64'h04000000_03000000,
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64'h00000000_73757063,
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64'h01000000_00657261,
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64'h622d656e_61697261,
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64'h2c687465_26000000,
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64'h10000000_03000000,
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64'h00766564_2d657261,
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64'h622d656e_61697261,
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64'h2c687465_1b000000,
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64'h14000000_03000000,
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64'h02000000_0f000000,
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64'h04000000_03000000,
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64'h02000000_00000000,
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64'h04000000_03000000,
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64'h00000000_01000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h0c040000_06010000,
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64'h00000000_10000000,
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64'h11000000_28000000,
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64'h44040000_38000000,
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64'h4a050000_edfe0dd0,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_ffdff06f,
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64'h10500073_03c58593,
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64'h00000597_f1402573,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00040067_07458593,
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64'h00000597_f1402573,
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64'h01f41413_00100413
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};
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logic [$clog2(RomSize)-1:0] addr_q;
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always_ff @(posedge clk_i) begin
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if (req_i) begin
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addr_q <= addr_i[$clog2(RomSize)-1+3:3];
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end
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end
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// this prevents spurious Xes from propagating into
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// the speculative fetch stage of the core
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assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
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endmodule
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