mirror of
https://github.com/openhwgroup/cva6.git
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135 lines
3.7 KiB
Python
Executable file
135 lines
3.7 KiB
Python
Executable file
#!/usr/bin/env python3
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""" Convert binary output of 'objcopy -O binary elfFile' into a system verilog module and
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a header file for simulation
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"""
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from string import Template
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import argparse
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import os.path
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import sys
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def parse():
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parser = argparse.ArgumentParser(description='Convert binary file to verilog rom')
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parser.add_argument('filename', metavar='filename', nargs=1,
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help='filename of input binary')
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args = parser.parse_args()
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file = args.filename[0]
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filename = os.path.splitext(file)[0]
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# check that file exists
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if not os.path.isfile(file):
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print("File {} does not exist.".format(filename))
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sys.exit(1)
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return filename
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LICENSE_TEMPLATE = """\
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/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: $filename.v
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*
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* Description: Auto-generated bootrom
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*/
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// Auto-generated code
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"""
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MODULE_TEMPLATE = """\
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module $filename (
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input logic clk_i,
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input logic req_i,
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = $size;
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const logic [RomSize-1:0][63:0] mem = {
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$content
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};
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logic [$$clog2(RomSize)-1:0] addr_q;
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always_ff @(posedge clk_i) begin
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if (req_i) begin
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addr_q <= addr_i[$$clog2(RomSize)-1+3:3];
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end
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end
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// this prevents spurious Xes from propagating into
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// the speculative fetch stage of the core
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assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
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endmodule
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"""
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c_var = """\
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// Auto-generated code
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const int reset_vec_size = $size;
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uint32_t reset_vec[reset_vec_size] = {
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$content
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};
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"""
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def read_bin(filename):
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with open(filename + ".img", 'rb') as f:
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rom = f.read()
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# align to 64 bit
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align = (int((len(rom) + 7) / 8 )) * 8
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for i in range(len(rom), align):
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rom += b"\x00"
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return rom
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def generate_h(filename, rom):
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""" Generate C header file for simulator """
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with open(filename + ".h", "w") as f:
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rom_str = ""
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# process in junks of 32 bit (4 byte)
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for i in range(0, int(len(rom)/4)):
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rom_str += " 0x" + bytes(reversed(rom[i*4:i*4+4])).hex() + ",\n"
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# remove the trailing comma
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rom_str = rom_str[:-2]
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s = Template(c_var)
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f.write(s.substitute(filename=filename, size=int(len(rom)/4), content=rom_str))
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f.close()
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def generate_sv(filename, rom):
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""" Generate SystemVerilog bootcode for FPGA and ASIC """
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with open(filename + ".sv", "w") as f:
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rom_str = ""
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rom = bytes(reversed(rom))
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# process in junks of 64 bit (8 byte)
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for i in range(int(len(rom)/8)):
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rom_str += " 64'h" + rom[i*8:i*8+4].hex() + "_" + rom[i*8+4:i*8+8].hex() + ",\n"
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# remove the trailing comma
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rom_str = rom_str[:-2]
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f.write(LICENSE_TEMPLATE)
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s = Template(MODULE_TEMPLATE)
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f.write(s.substitute(filename=filename, size=int(len(rom)/8), content=rom_str))
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def main():
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filename = parse()
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rom = read_bin(filename)
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generate_sv(filename, rom)
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generate_h(filename, rom)
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if __name__ == "__main__":
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main()
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