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44 lines
1.4 KiB
ReStructuredText
44 lines
1.4 KiB
ReStructuredText
..
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Copyright (c) 2023 OpenHW Group
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Copyright (c) 2023 Thales DIS design services SAS
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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.. Level 1
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=======
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Level 2
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-------
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Level 3
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~~~~~~~
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Level 4
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^^^^^^^
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.. _cva6_pmp:
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PMP
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===
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The CVA6 includes a Physical Memory Protection (PMP) unit. The PMP is both
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statically and dynamically configurable. The static configuration is performed
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through the top level parameters ``CVA6Cfg.NrPMPEntries``. The dynamic
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configuration is performed through the CSRs described in Control and Status
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Registers. A maximum of 16 PMP entries are supported.
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All PMP CSRs are always implemented, but CSRs (or bitfields of CSRs) related to
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PMP entries with number ``CVA6Cfg.NrPMPEntries`` and above are hardwired to
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zero. All PMPs reset to zero.
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When the ``L`` (Lock) bit is set, PMPs are also enforced in M-mode.
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The PMP grain is ``2**G+2``. Only a PMP granularity of 8 bytes (``G=1``) is
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supported in CVA6. PMP address length is equal to the processors physical
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address length. Since ``G=1`` the ``NA4`` modes is not selectable.
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Writes to ``pmpaddr`` are WARL and depend on the address mode. For naturally
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aligned power-of 2 addressing mode (``NAPOT``) it is set to ``1``, for top
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boundary of an arbitrary range (``TOR``) or ``OFF`` it is set to ``0``.
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If, on write to `pmpcfgX`, ``R=0`` and ``W=1`` are set the CSR will not be
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updated.
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