github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-19 03:44:46 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
cva6/docs/common
History
Exact
André Sintzoff 21506e4c66
Some checks are pending
bender-up-to-date / bender-up-to-date (push) Waiting to run
Details
ci / build-riscv-tests (push) Waiting to run
Details
ci / execute-riscv64-tests (push) Blocked by required conditions
Details
ci / execute-riscv32-tests (push) Blocked by required conditions
Details
docs: add CV32A60X configuration in RISC-V ISA manual (#2838) 
* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
* in opcode map, write not used when corresponding extension is disabled
* use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-03-19 00:03:00 +01:00
..
config_define.adoc docs: add CV32A60X configuration in RISC-V ISA manual (#2838) 2025-03-19 00:03:00 +01:00