mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-23 13:47:13 -04:00
21506e4c66
* docs: spec_builder.py: add missing extensions * docs: fix unpriv manual (opcode map, Zcmop) * in opcode map, write not used when corresponding extension is disabled * use correct condition for Zcmop extension * docs: remove PMP chapter when no PMP * docs: add tailored RISC-V ISA manual for CV32A60X configuration Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
81 lines
1.2 KiB
Text
81 lines
1.2 KiB
Text
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ifeval::["{ohg-config}"=="CV32A60X"]
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:archi-CVA6:
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:archi-CV32A60X:
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// specify that it is a custom architecture
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:archi-not-default:
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endif::[]
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ifeval::["{ohg-config}"=="CV32A65X"]
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:archi-CVA6:
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:archi-CV32A65X:
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// specify that it is a custom architecture
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:archi-not-default:
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endif::[]
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ifeval::["{ohg-config}"=="CV64A6_MMU"]
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:archi-CVA6:
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:archi-CV64A6_MMU:
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// specify that it is a custom architecture
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:archi-not-default:
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endif::[]
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ifndef::archi-not-default[]
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:archi-default:
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endif::[]
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ifeval::[{RVS} == true]
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:RVS-true:
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endif::[]
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ifeval::[{RVU} == true]
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:RVU-true:
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endif::[]
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ifeval::[{XLEN} == 32]
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:XLEN-32:
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endif::[]
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ifeval::[{XLEN} == 64]
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:XLEN-64:
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endif::[]
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ifeval::[{RVZsmcntrpmf} == true]
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:RVZsmcntrpmf-true:
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endif::[]
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ifeval::[{RVC} == true]
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:RVC-true:
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endif::[]
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ifeval::[{MTvecDirectEn} == true]
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:MTvecDirectEn-true:
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endif::[]
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ifeval::[{MTvalEn} == true]
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:MTvalEn-true:
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endif::[]
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ifeval::[{RVZsmepmp} == true]
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:RVZsmepmp-true:
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endif::[]
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ifeval::[{DCacheEn} == true]
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:DCacheEn-true:
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endif::[]
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ifeval::[{RVA} == true]
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:RVA-true:
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endif::[]
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ifeval::[{RVZsmdbltrp} == true]
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:RVZsmdbltrp-true:
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endif::[]
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ifeval::[{RVZssdbltrp} == true]
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:RVZssdbltrp-true:
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endif::[]
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ifeval::[{RVZicfilp} == true]
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:RVZicfilp-true:
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endif::[]
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