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ab2283c075
Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters). As of now, they are committed to the repository and can be out of sync with the code. This PR removes them from the repository and freshly generates them from the code when building HTML files. This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
34 lines
1.4 KiB
Text
34 lines
1.4 KiB
Text
////
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Copyright 2022 Thales DIS design services SAS
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Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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You may obtain a copy of the License at https://solderpad.org/licenses/
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Original Author: Jean-Roch COULON - Thales
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////
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[[architecture-and-modules]]
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Architecture and Modules
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------------------------
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The {ohg-config} is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
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For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
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The {ohg-config} subsystem is composed of 8 modules.
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image:subsystems.png[{ohg-config} modules]
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Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. And CACHES implements the instruction and data caches and CSRFILE contains registers.
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image:{ohg-config}_subsystems.png[{ohg-config} pipeline and modules]
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include::cva6_frontend.adoc[]
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include::cva6_id_stage.adoc[]
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include::cva6_issue_stage.adoc[]
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include::cva6_execute.adoc[]
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include::cva6_commit_stage.adoc[]
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include::cva6_controller.adoc[]
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include::cva6_csr_regfile.adoc[]
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include::cva6_caches.adoc[]
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