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doc: keep documentation in sync with the code (#2558)
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Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
As of now, they are committed to the repository and can be out of sync with the code.

This PR removes them from the repository and freshly generates them from the code when building HTML files.

This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
This commit is contained in:
slgth 2024-10-25 12:27:09 +02:00 • committed by GitHub
parent 01c636dd55
commit ab2283c075
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53 changed files with 204 additions and 79451 deletions
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.readthedocs.yaml
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@ -8,6 +8,14 @@ build:
os: "ubuntu-20.04"
tools:
python: "3.9"
nodejs: "20"
ruby: "3.3"
jobs:
post-install:
- npm install docs/riscv-isa/riscv-isa-manual/dependencies
- gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile
pre-build:
- make -C docs prepare
# Build from the docs directory with Sphinx
sphinx:

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config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
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@ -16,7 +16,6 @@
|M | RV32M Multiplication and Division Instructions | the standard integer multiplication and division instruction extension, which is named “M” and contains instructions that multiply or divide values held in two integer registers.
|C | RV32C Compressed Instructions | RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when: the immediate or address offset is small; one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); the destination register and the first source register are identical; the registers used are the 8 most popular ones.The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions will no longer raise an instruction misaligned exception
|Zicsr | RV32Zicsr Control and Status Register Instructions | All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.
|Zifencei | RVZifencei Instruction Fetch Fence | FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart.Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to it instruction fetches.
|Zcb | RV32Zcb Code Size Reduction Instructions | Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions.
|Zba | RVZba Address generation instructions | The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw added in this extension can be used when the index is to be interpreted as an unsigned word.
|Zbb | RVZbb Basic bit-manipulation | The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name.
@ -133,14 +132,6 @@
| CSRRCI | csrrci rd, csr, uimm[4:0] | t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. | Control and Status Register Operations
|===
==== RVZifencei Instruction Fetch Fence
|===
| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name
| FENCE.I | fence.i | Fence(Store, Fetch) | NONE | NONE | The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. | Fetch Fence Operations
|===
==== RV32Zcb Code Size Reduction Instructions
|===

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*~
/_build
*.swp
*.html

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:ohg-config: CV32A65X
:XLEN: 32
:RVA: false
:RVC: true
:RVD: false
:RVE: false
:RVF: false
:RVH: false
:RVQ: false
:RVS: false
:RVU: false
:RVV: false
:RVZabha: false
:RVZacas: false
:RVZawrs: false
:RVZfa: false
:RVZfbf-RZvfbf: false
:RVZfh: false
:RVZfinx: false
:RVZicbo: false
:RVZicfilp: false
:RVZicfiss: false
:RVZicond: false
:RVZifencei: false
:RVZihintntl: false
:RVZihintpause: false
:RVZihpm: false
:RVZimop: false
:RVZk: false
:RVZpm: false
:RVZsmcdeleg: false
:RVZsmcntrpmf: false
:RVZsmcsrind-RVZsscsrind: false
:RVZsmdbltrp: false
:RVZsmepmp: false
:RVZsmmpm: false
:RVZsmrnmi: false
:RVZsmstateen: false
:RVZsscofpmf: false
:RVZssdbltrp: false
:RVZsstc: false
:RVZtso: false
:RVZvk: false
:SV: SV0
:DCacheEn: false
:MTvalEn: false
:MTvecDirectEn: true
:note: false
:DebugEn: false
:MmuPresent: false

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[cv32a65x_PARAMETERS]]
.cv32a65x parameter configuration
|===
|Name | description | description
|XLEN | General Purpose Register Size (in bits) | 32
|RVA | Atomic RISC-V extension | False
|RVB | Bit manipulation RISC-V extension | True
|RVV | Vector RISC-V extension | False
|RVC | Compress RISC-V extension | True
|RVH | Hypervisor RISC-V extension | False
|RVZCB | Zcb RISC-V extension | True
|RVZCMP | Zcmp RISC-V extension | False
|RVZiCond | Zicond RISC-V extension | False
|RVZicntr | Zicntr RISC-V extension | False
|RVZihpm | Zihpm RISC-V extension | False
|RVF | Floating Point | False
|RVD | Floating Point | False
|XF16 | Non standard 16bits Floating Point extension | False
|XF16ALT | Non standard 16bits Floating Point Alt extension | False
|XF8 | Non standard 8bits Floating Point extension | False
|XFVec | Non standard Vector Floating Point extension | False
|PerfCounterEn | Perf counters | False
|MmuPresent | MMU | False
|RVS | Supervisor mode | False
|RVU | User mode | False
|DebugEn | Debug support | False
|DmBaseAddress | Base address of the debug module | 0x0
|HaltAddress | Address to jump when halt request | 0x800
|ExceptionAddress | Address to jump when exception | 0x808
|TvalEn | Tval Support Enable | False
|DirectVecOnly | MTVEC CSR supports only direct mode | True
|NrPMPEntries | PMP entries number | 8
|PMPCfgRstVal | PMP CSR configuration reset values | [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]
|PMPAddrRstVal | PMP CSR address reset values | [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]
|PMPEntryReadOnly | PMP CSR read-only bits | 0
|NrNonIdempotentRules | PMA non idempotent rules number | 0
|NonIdempotentAddrBase | PMA NonIdempotent region base address | [0b0, 0b0]
|NonIdempotentLength | PMA NonIdempotent region length | [0b0, 0b0]
|NrExecuteRegionRules | PMA regions with execute rules number | 0
|ExecuteRegionAddrBase | PMA Execute region base address | [0x80000000, 0x10000, 0x0]
|ExecuteRegionLength | PMA Execute region address base | [0x40000000, 0x10000, 0x1000]
|NrCachedRegionRules | PMA regions with cache rules number | 1
|CachedRegionAddrBase | PMA cache region base address | [0x80000000]
|CachedRegionLength | PMA cache region rules | [0x40000000]
|CvxifEn | CV-X-IF coprocessor interface enable | True
|NOCType | NOC bus type | config_pkg::NOC_TYPE_AXI4_ATOP
|AxiAddrWidth | AXI address width | 64
|AxiDataWidth | AXI data width | 64
|AxiIdWidth | AXI ID width | 4
|AxiUserWidth | AXI User width | 32
|AxiBurstWriteEn | AXI burst in write | False
|MemTidWidth | TODO | 4
|IcacheByteSize | Instruction cache size (in bytes) | 2048
|IcacheSetAssoc | Instruction cache associativity (number of ways) | 2
|IcacheLineWidth | Instruction cache line width | 128
|DCacheType | Cache Type | config_pkg::HPDCACHE
|DcacheIdWidth | Data cache ID | 1
|DcacheByteSize | Data cache size (in bytes) | 2028
|DcacheSetAssoc | Data cache associativity (number of ways) | 2
|DcacheLineWidth | Data cache line width | 128
|DataUserEn | User field on data bus enable | 1
|WtDcacheWbufDepth | Write-through data cache write buffer depth | 8
|FetchUserEn | User field on fetch bus enable | 1
|FetchUserWidth | Width of fetch user field | 32
|FpgaEn | Is FPGA optimization of CV32A6 | False
|TechnoCut | Is Techno Cut instanciated | True
|SuperscalarEn | Enable superscalar* with 2 issue ports and 2 commit ports. | True
|NrCommitPorts | Number of commit ports. Forced to 2 if SuperscalarEn. | 1
|NrLoadPipeRegs | Load cycle latency number | 0
|NrStorePipeRegs | Store cycle latency number | 0
|NrScoreboardEntries | Scoreboard length | 8
|NrLoadBufEntries | Load buffer entry buffer | 2
|MaxOutstandingStores | Maximum number of outstanding stores | 7
|RASDepth | Return address stack depth | 2
|BTBEntries | Branch target buffer entries | 0
|BHTEntries | Branch history entries | 32
|InstrTlbEntries | MMU instruction TLB entries | 2
|DataTlbEntries | MMU data TLB entries | 2
|UseSharedTlb | MMU option to use shared TLB | True
|SharedTlbDepth | MMU depth of shared TLB | 64
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_alu_ports]]
.*alu module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`fu_data_i` | in | FU data needed to execute instruction | ISSUE_STAGE | fu_data_t
|`result_o` | out | ALU result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`alu_branch_res_o` | out | ALU branch compare result | branch_unit | logic
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_bht_ports]]
.*bht module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`vpc_i` | in | Virtual PC | CACHE | logic[CVA6Cfg.VLEN-1:0]
|`bht_update_i` | in | Update bht with resolved address | EXECUTE | bht_update_t
|`bht_prediction_o` | out | Prediction from bht | FRONTEND | ariane_pkg::bht_prediction_t[CVA6Cfg.INSTR_PER_FETCH-1:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
For any HW configuration,::
* `flush_bp_i` input is tied to 0
As DebugEn = False,::
* `debug_mode_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_branch_unit_ports]]
.*branch_unit module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`fu_data_i` | in | FU data needed to execute instruction | ISSUE_STAGE | fu_data_t
|`pc_i` | in | Instruction PC | ISSUE_STAGE | logic[CVA6Cfg.VLEN-1:0]
|`is_compressed_instr_i` | in | Instruction is compressed | ISSUE_STAGE | logic
|`branch_valid_i` | in | Branch unit instruction is valid | ISSUE_STAGE | logic
|`branch_comp_res_i` | in | ALU branch compare result | ALU | logic
|`branch_result_o` | out | Brach unit result | ISSUE_STAGE | logic[CVA6Cfg.VLEN-1:0]
|`branch_predict_i` | in | Information of branch prediction | ISSUE_STAGE | branchpredict_sbe_t
|`resolved_branch_o` | out | Signaling that we resolved the branch | ISSUE_STAGE | bp_resolve_t
|`resolve_branch_o` | out | Branch is resolved, new entries can be accepted by scoreboard | ID_STAGE | logic
|`branch_exception_o` | out | Branch exception out | TO_BE_COMPLETED | exception_t
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVH = False,::
* `v_i` input is tied to 0
As DebugEn = False,::
* `debug_mode_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_btb_ports]]
.*btb module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`vpc_i` | in | Virtual PC | CACHE | logic[CVA6Cfg.VLEN-1:0]
|`btb_update_i` | in | Update BTB with resolved address | EXECUTE | btb_update_t
|`btb_prediction_o` | out | BTB Prediction | FRONTEND | btb_prediction_t[CVA6Cfg.INSTR_PER_FETCH-1:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
For any HW configuration,::
* `flush_bp_i` input is tied to 0
As DebugEn = False,::
* `debug_mode_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_commit_stage_ports]]
.*commit_stage module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`halt_i` | in | Request to halt the core | CONTROLLER | logic
|`flush_dcache_i` | in | request to flush dcache, also flush the pipeline | CACHE | logic
|`exception_o` | out | TO_BE_COMPLETED | EX_STAGE | exception_t
|`commit_instr_i` | in | The instruction we want to commit | ISSUE_STAGE | scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
|`commit_drop_i` | in | The instruction is cancelled | ISSUE_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`commit_ack_o` | out | Acknowledge that we are indeed committing | ISSUE_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`commit_macro_ack_o` | out | Acknowledge that we are indeed committing | CSR_REGFILE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`waddr_o` | out | Register file write address | ISSUE_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
|`wdata_o` | out | Register file write data | ISSUE_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0]
|`we_gpr_o` | out | Register file write enable | ISSUE_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`we_fpr_o` | out | Floating point register enable | ISSUE_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`pc_o` | out | TO_BE_COMPLETED | FRONTEND_CSR_REGFILE | logic[CVA6Cfg.VLEN-1:0]
|`csr_op_o` | out | Decoded CSR operation | CSR_REGFILE | fu_op
|`csr_wdata_o` | out | Data to write to CSR | CSR_REGFILE | logic[CVA6Cfg.XLEN-1:0]
|`csr_rdata_i` | in | Data to read from CSR | CSR_REGFILE | logic[CVA6Cfg.XLEN-1:0]
|`csr_exception_i` | in | Exception or interrupt occurred in CSR stage (the same as commit) | CSR_REGFILE | exception_t
|`commit_lsu_o` | out | Commit the pending store | EX_STAGE | logic
|`commit_lsu_ready_i` | in | Commit buffer of LSU is ready | EX_STAGE | logic
|`commit_tran_id_o` | out | Transaction id of first commit port | ID_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`no_st_pending_i` | in | no store is pending | EX_STAGE | logic
|`commit_csr_o` | out | Commit the pending CSR instruction | EX_STAGE | logic
|`flush_commit_o` | out | Request a pipeline flush | CONTROLLER | logic
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVF = 0,::
* `dirty_fp_state_o` output is tied to 0
* `csr_write_fflags_o` output is tied to 0
As DebugEn = False,::
* `single_step_i` input is tied to 0
As RVA = False,::
* `amo_resp_i` input is tied to 0
* `amo_valid_commit_o` output is tied to 0
As FenceEn = 0,::
* `fence_i_o` output is tied to 0
* `fence_o` output is tied to 0
As RVS = False,::
* `sfence_vma_o` output is tied to 0
As RVH = False,::
* `hfence_vvma_o` output is tied to 0
* `hfence_gvma_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_compressed_decoder_ports]]
.*compressed_decoder module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`instr_i` | in | Input instruction coming from fetch stage | FRONTEND | logic[31:0]
|`instr_o` | out | Output instruction in uncompressed format | decoder | logic[31:0]
|`illegal_instr_o` | out | Input instruction is illegal | decoder | logic
|`is_macro_instr_o` | out | Output instruction is macro | decoder | logic
|`is_compressed_o` | out | Output instruction is compressed | decoder | logic
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_controller_ports]]
.*controller module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`set_pc_commit_o` | out | Set PC om PC Gen | FRONTEND | logic
|`flush_if_o` | out | Flush the IF stage | FRONTEND | logic
|`flush_unissued_instr_o` | out | Flush un-issued instructions of the scoreboard | FRONTEND | logic
|`flush_id_o` | out | Flush ID stage | ID_STAGE | logic
|`flush_ex_o` | out | Flush EX stage | EX_STAGE | logic
|`flush_bp_o` | out | Flush branch predictors | FRONTEND | logic
|`flush_icache_o` | out | Flush ICache | CACHE | logic
|`flush_dcache_o` | out | Flush DCache | CACHE | logic
|`flush_dcache_ack_i` | in | Acknowledge the whole DCache Flush | CACHE | logic
|`halt_csr_i` | in | Halt request from CSR (WFI instruction) | CSR_REGFILE | logic
|`halt_o` | out | Halt signal to commit stage | COMMIT_STAGE | logic
|`eret_i` | in | Return from exception | CSR_REGFILE | logic
|`ex_valid_i` | in | We got an exception, flush the pipeline | FRONTEND | logic
|`resolved_branch_i` | in | We got a resolved branch, check if we need to flush the front-end | EX_STAGE | bp_resolve_t
|`flush_csr_i` | in | We got an instruction which altered the CSR, flush the pipeline | CSR_REGFILE | logic
|`flush_commit_i` | in | Flush request from commit stage | COMMIT_STAGE | logic
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVH = False,::
* `v_i` input is tied to 0
* `flush_tlb_vvma_o` output is tied to 0
* `flush_tlb_gvma_o` output is tied to 0
* `hfence_vvma_i` input is tied to 0
* `hfence_gvma_i` input is tied to 0
As MMUPresent = 0,::
* `flush_tlb_o` output is tied to 0
As EnableAccelerator = 0,::
* `halt_acc_i` input is tied to 0
* `flush_acc_i` input is tied to 0
As DebugEn = False,::
* `set_debug_pc_i` input is tied to 0
As FenceEn = 0,::
* `fence_i_i` input is tied to 0
* `fence_i` input is tied to 0
As RVS = False,::
* `sfence_vma_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_csr_buffer_ports]]
.*csr_buffer module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Flush CSR | CONTROLLER | logic
|`fu_data_i` | in | FU data needed to execute instruction | ISSUE_STAGE | fu_data_t
|`csr_ready_o` | out | CSR FU is ready | ISSUE_STAGE | logic
|`csr_valid_i` | in | CSR instruction is valid | ISSUE_STAGE | logic
|`csr_result_o` | out | CSR buffer result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`csr_commit_i` | in | commit the pending CSR OP | TO_BE_COMPLETED | logic
|`csr_addr_o` | out | CSR address to write | COMMIT_STAGE | logic[11:0]
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_csr_regfile_ports]]
.*csr_regfile module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`time_irq_i` | in | Timer threw a interrupt | SUBSYSTEM | logic
|`flush_o` | out | send a flush request out when a CSR with a side effect changes | CONTROLLER | logic
|`halt_csr_o` | out | halt requested | CONTROLLER | logic
|`commit_instr_i` | in | Instruction to be committed | ID_STAGE | scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
|`commit_ack_i` | in | Commit acknowledged a instruction -> increase instret CSR | COMMIT_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`boot_addr_i` | in | Address from which to start booting, mtvec is set to the same address | SUBSYSTEM | logic[CVA6Cfg.VLEN-1:0]
|`hart_id_i` | in | Hart id in a multicore environment (reflected in a CSR) | SUBSYSTEM | logic[CVA6Cfg.XLEN-1:0]
|`ex_i` | in | We've got an exception from the commit stage, take it | COMMIT_STAGE | exception_t
|`csr_op_i` | in | Operation to perform on the CSR file | COMMIT_STAGE | fu_op
|`csr_addr_i` | in | Address of the register to read/write | EX_STAGE | logic[11:0]
|`csr_wdata_i` | in | Write data in | COMMIT_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`csr_rdata_o` | out | Read data out | COMMIT_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`pc_i` | in | PC of instruction accessing the CSR | COMMIT_STAGE | logic[CVA6Cfg.VLEN-1:0]
|`csr_exception_o` | out | attempts to access a CSR without appropriate privilege | COMMIT_STAGE | exception_t
|`epc_o` | out | Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`eret_o` | out | Return from exception, set the PC of epc_o | FRONTEND | logic
|`trap_vector_base_o` | out | Output base of exception vector, correct CSR is output (mtvec, stvec) | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`irq_ctrl_o` | out | interrupt management to id stage | ID_STAGE | irq_ctrl_t
|`irq_i` | in | external interrupt in | SUBSYSTEM | logic[1:0]
|`ipi_i` | in | inter processor interrupt -> connected to machine mode sw | SUBSYSTEM | logic
|`icache_en_o` | out | L1 ICache Enable | CACHE | logic
|`dcache_en_o` | out | L1 DCache Enable | CACHE | logic
|`rvfi_csr_o` | out | none | none | rvfi_probes_csr_t
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVF = 0,::
* `dirty_fp_state_i` input is tied to 0
* `csr_write_fflags_i` input is tied to 0
* `fs_o` output is tied to 0
* `fflags_o` output is tied to 0
* `frm_o` output is tied to 0
* `fprec_o` output is tied to 0
As EnableAccelerator = 0,::
* `dirty_v_state_i` input is tied to 0
* `acc_fflags_ex_i` input is tied to 0
* `acc_fflags_ex_valid_i` input is tied to 0
* `acc_cons_en_o` output is tied to 0
* `pmpcfg_o` output is tied to 0
* `pmpaddr_o` output is tied to 0
As PRIV = MachineOnly,::
* `priv_lvl_o` output is tied to MachineMode
* `ld_st_priv_lvl_o` output is tied to MAchineMode
* `tvm_o` output is tied to 0
* `tw_o` output is tied to 0
* `tsr_o` output is tied to 0
As RVH = False,::
* `v_o` output is tied to 0
* `vfs_o` output is tied to 0
* `en_g_translation_o` output is tied to 0
* `en_ld_st_g_translation_o` output is tied to 0
* `ld_st_v_o` output is tied to 0
* `csr_hs_ld_st_inst_i` input is tied to 0
* `vs_sum_o` output is tied to 0
* `vmxr_o` output is tied to 0
* `vsatp_ppn_o` output is tied to 0
* `vs_asid_o` output is tied to 0
* `hgatp_ppn_o` output is tied to 0
* `vmid_o` output is tied to 0
* `vtw_o` output is tied to 0
* `hu_o` output is tied to 0
As RVV = False,::
* `vs_o` output is tied to 0
As RVS = False,::
* `en_translation_o` output is tied to 0
* `en_ld_st_translation_o` output is tied to 0
* `sum_o` output is tied to 0
* `mxr_o` output is tied to 0
* `satp_ppn_o` output is tied to 0
* `asid_o` output is tied to 0
As DebugEn = False,::
* `debug_req_i` input is tied to 0
* `set_debug_pc_o` output is tied to 0
* `debug_mode_o` output is tied to 0
* `single_step_o` output is tied to 0
As PerfCounterEn = 0,::
* `perf_addr_o` output is tied to 0
* `perf_data_o` output is tied to 0
* `perf_data_i` input is tied to 0
* `perf_we_o` output is tied to 0
* `mcountinhibit_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_cva6_ports]]
.*cva6 module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`boot_addr_i` | in | Reset boot address | SUBSYSTEM | logic[CVA6Cfg.VLEN-1:0]
|`hart_id_i` | in | Hard ID reflected as CSR | SUBSYSTEM | logic[CVA6Cfg.XLEN-1:0]
|`irq_i` | in | Level sensitive (async) interrupts | SUBSYSTEM | logic[1:0]
|`ipi_i` | in | Inter-processor (async) interrupt | SUBSYSTEM | logic
|`time_irq_i` | in | Timer (async) interrupt | SUBSYSTEM | logic
|`cvxif_req_o` | out | CVXIF request | SUBSYSTEM | cvxif_req_t
|`cvxif_resp_i` | in | CVXIF response | SUBSYSTEM | cvxif_resp_t
|`noc_req_o` | out | noc request, can be AXI or OpenPiton | SUBSYSTEM | noc_req_t
|`noc_resp_i` | in | noc response, can be AXI or OpenPiton | SUBSYSTEM | noc_resp_t
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As DebugEn = False,::
* `debug_req_i` input is tied to 0
As IsRVFI = 0,::
* `rvfi_probes_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_cva6_hpdcache_subsystem_ports]]
.*cva6_hpdcache_subsystem module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`noc_req_o` | out | noc request, can be AXI or OpenPiton | SUBSYSTEM | noc_req_t
|`noc_resp_i` | in | noc response, can be AXI or OpenPiton | SUBSYSTEM | noc_resp_t
|`icache_en_i` | in | Instruction cache enable | CSR_REGFILE | logic
|`icache_flush_i` | in | Flush the instruction cache | CONTROLLER | logic
|`icache_areq_i` | in | Input address translation request | EX_STAGE | icache_areq_t
|`icache_areq_o` | out | Output address translation request | EX_STAGE | icache_arsp_t
|`icache_dreq_i` | in | Input data translation request | FRONTEND | icache_dreq_t
|`icache_dreq_o` | out | Output data translation request | FRONTEND | icache_drsp_t
|`dcache_enable_i` | in | Data cache enable | CSR_REGFILE | logic
|`dcache_flush_i` | in | Data cache flush | CONTROLLER | logic
|`dcache_flush_ack_o` | out | Flush acknowledge | CONTROLLER | logic
|`dcache_amo_req_i` | in | AMO request | EX_STAGE | ariane_pkg::amo_req_t
|`dcache_amo_resp_o` | out | AMO response | EX_STAGE | ariane_pkg::amo_resp_t
|`dcache_req_ports_i` | in | Data cache input request ports | EX_STAGE | dcache_req_i_t[NumPorts-1:0]
|`dcache_req_ports_o` | out | Data cache output request ports | EX_STAGE | dcache_req_o_t[NumPorts-1:0]
|`wbuffer_empty_o` | out | Write buffer status to know if empty | EX_STAGE | logic
|`wbuffer_not_ni_o` | out | Write buffer status to know if not non idempotent | EX_STAGE | logic
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As PerfCounterEn = 0,::
* `icache_miss_o` output is tied to 0
* `dcache_miss_o` output is tied to 0
For any HW configuration,::
* `dcache_cmo_req_i` input is tied to 0
* `dcache_cmo_resp_o` output is tied to open
* `hwpf_base_set_i` input is tied to 0
* `hwpf_base_i` input is tied to 0
* `hwpf_base_o` output is tied to 0
* `hwpf_param_set_i` input is tied to 0
* `hwpf_param_i` input is tied to 0
* `hwpf_param_o` output is tied to 0
* `hwpf_throttle_set_i` input is tied to 0
* `hwpf_throttle_i` input is tied to 0
* `hwpf_throttle_o` output is tied to 0
* `hwpf_status_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_cvxif_fu_ports]]
.*cvxif_fu module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`x_valid_i` | in | CVXIF instruction is valid | ISSUE_STAGE | logic
|`x_trans_id_i` | in | Transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`x_illegal_i` | in | Instruction is illegal, determined during CVXIF issue transaction | ISSUE_STAGE | logic
|`x_off_instr_i` | in | Offloaded instruction | ISSUE_STAGE | logic[31:0]
|`x_ready_o` | out | CVXIF is ready | ISSUE_STAGE | logic
|`x_trans_id_o` | out | CVXIF result transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`x_exception_o` | out | CVXIF exception | ISSUE_STAGE | exception_t
|`x_result_o` | out | CVXIF FU result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`x_valid_o` | out | CVXIF result valid | ISSUE_STAGE | logic
|`x_we_o` | out | CVXIF write enable | ISSUE_STAGE | logic
|`x_rd_o` | out | CVXIF destination register | ISSUE_STAGE | logic[4:0]
|`result_valid_i` | in | none | none | logic
|`result_i` | in | none | none | x_result_t
|`result_ready_o` | out | none | none | logic
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_decoder_ports]]
.*decoder module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`pc_i` | in | PC from fetch stage | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`is_compressed_i` | in | Is a compressed instruction | compressed_decoder | logic
|`compressed_instr_i` | in | Compressed form of instruction | FRONTEND | logic[15:0]
|`is_illegal_i` | in | Illegal compressed instruction | compressed_decoder | logic
|`instruction_i` | in | Instruction from fetch stage | FRONTEND | logic[31:0]
|`is_macro_instr_i` | in | Is a macro instruction | macro_decoder | logic
|`is_last_macro_instr_i` | in | Is a last macro instruction | macro_decoder | logic
|`is_double_rd_macro_instr_i` | in | Is mvsa01/mva01s macro instruction | macro_decoder | logic
|`branch_predict_i` | in | Is a branch predict instruction | FRONTEND | branchpredict_sbe_t
|`ex_i` | in | If an exception occured in fetch stage | FRONTEND | exception_t
|`irq_i` | in | Level sensitive (async) interrupts | SUBSYSTEM | logic[1:0]
|`irq_ctrl_i` | in | Interrupt control status | CSR_REGFILE | irq_ctrl_t
|`instruction_o` | out | Instruction to be added to scoreboard entry | ISSUE_STAGE | scoreboard_entry_t
|`orig_instr_o` | out | Instruction | ISSUE_STAGE | logic[31:0]
|`is_control_flow_instr_o` | out | Is a control flow instruction | ISSUE_STAGE | logic
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As DebugEn = False,::
* `debug_req_i` input is tied to 0
* `debug_mode_i` input is tied to 0
As PRIV = MachineOnly,::
* `priv_lvl_i` input is tied to MachineMode
* `tvm_i` input is tied to 0
* `tw_i` input is tied to 0
* `tsr_i` input is tied to 0
As RVH = False,::
* `v_i` input is tied to 0
* `vfs_i` input is tied to 0
* `vtw_i` input is tied to 0
* `hu_i` input is tied to 0
As RVF = 0,::
* `fs_i` input is tied to 0
* `frm_i` input is tied to 0
As RVV = False,::
* `vs_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_ex_stage_ports]]
.*ex_stage module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Fetch flush request | CONTROLLER | logic
|`rs1_forwarding_i` | in | rs1 forwarding | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0]
|`rs2_forwarding_i` | in | rs2 forwarding | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0]
|`fu_data_i` | in | FU data useful to execute instruction | ISSUE_STAGE | fu_data_t[CVA6Cfg.NrIssuePorts-1:0]
|`pc_i` | in | PC of the current instruction | ISSUE_STAGE | logic[CVA6Cfg.VLEN-1:0]
|`is_compressed_instr_i` | in | Report whether instruction is compressed | ISSUE_STAGE | logic
|`flu_result_o` | out | Fixed Latency Unit result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`flu_trans_id_o` | out | ID of the scoreboard entry at which a=to write back | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`flu_exception_o` | out | Fixed Latency Unit exception | ISSUE_STAGE | exception_t
|`flu_ready_o` | out | FLU is ready | ISSUE_STAGE | logic
|`flu_valid_o` | out | FLU result is valid | ISSUE_STAGE | logic
|`alu_valid_i` | in | ALU instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`branch_valid_i` | in | Branch unit instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`branch_predict_i` | in | Information of branch prediction | ISSUE_STAGE | branchpredict_sbe_t
|`resolved_branch_o` | out | The branch engine uses the write back from the ALU | several_modules | bp_resolve_t
|`resolve_branch_o` | out | Signaling that we resolved the branch | ISSUE_STAGE | logic
|`csr_valid_i` | in | CSR instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`csr_addr_o` | out | CSR address to write | COMMIT_STAGE | logic[11:0]
|`csr_commit_i` | in | CSR commit | COMMIT_STAGE | logic
|`mult_valid_i` | in | MULT instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`lsu_ready_o` | out | LSU is ready | ISSUE_STAGE | logic
|`lsu_valid_i` | in | LSU instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`load_valid_o` | out | Load result is valid | ISSUE_STAGE | logic
|`load_result_o` | out | Load result valid | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`load_trans_id_o` | out | Load instruction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`load_exception_o` | out | Exception generated by load instruction | ISSUE_STAGE | exception_t
|`store_valid_o` | out | Store result is valid | ISSUe_STAGE | logic
|`store_result_o` | out | Store result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`store_trans_id_o` | out | Store instruction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`store_exception_o` | out | Exception generated by store instruction | ISSUE_STAGE | exception_t
|`lsu_commit_i` | in | LSU commit | COMMIT_STAGE | logic
|`lsu_commit_ready_o` | out | Commit queue ready to accept another commit request | COMMIT_STAGE | logic
|`commit_tran_id_i` | in | Commit transaction ID | COMMIT_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`no_st_pending_o` | out | TO_BE_COMPLETED | COMMIT_STAGE | logic
|`alu2_valid_i` | in | ALU2 instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`x_valid_i` | in | CVXIF instruction is valid | ISSUE_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`x_ready_o` | out | CVXIF is ready | ISSUE_STAGE | logic
|`x_off_instr_i` | in | none | none | logic[31:0]
|`x_trans_id_o` | out | CVXIF transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`x_exception_o` | out | CVXIF exception | ISSUE_STAGE | exception_t
|`x_result_o` | out | CVXIF result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`x_valid_o` | out | CVXIF result valid | ISSUE_STAGE | logic
|`x_we_o` | out | CVXIF write enable | ISSUE_STAGE | logic
|`x_rd_o` | out | CVXIF destination register | ISSUE_STAGE | logic[4:0]
|`x_result_valid_i` | in | CVXIF Result interface | SUBSYSTEM | logic
|`x_result_i` | in | none | none | x_result_t
|`x_result_ready_o` | out | none | none | logic
|`x_transaction_rejected_i` | in | CVXIF Issue transaction rejected -> illegal instruction | ISSUE_STAGE | logic
|`icache_areq_i` | in | icache translation response | CACHE | icache_arsp_t
|`icache_areq_o` | out | icache translation request | CACHE | icache_areq_t
|`dcache_req_ports_i` | in | Data cache request ouput | CACHE | dcache_req_o_t[2:0]
|`dcache_req_ports_o` | out | Data cache request input | CACHE | dcache_req_i_t[2:0]
|`dcache_wbuffer_empty_i` | in | Write buffer is empty | CACHE | logic
|`dcache_wbuffer_not_ni_i` | in | TO_BE_COMPLETED | CACHE | logic
|`pmpcfg_i` | in | Report the PMP configuration | CSR_REGFILE | riscv::pmpcfg_t[CVA6Cfg.NrPMPEntries-1:0]
|`pmpaddr_i` | in | Report the PMP addresses | CSR_REGFILE | logic[CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As DebugEn = False,::
* `debug_mode_i` input is tied to 0
As RVH = False,::
* `tinst_i` input is tied to 0
* `enable_g_translation_i` input is tied to 0
* `en_ld_st_g_translation_i` input is tied to 0
* `flush_tlb_vvma_i` input is tied to 0
* `flush_tlb_gvma_i` input is tied to 0
* `v_i` input is tied to 0
* `ld_st_v_i` input is tied to 0
* `csr_hs_ld_st_inst_o` output is tied to 0
* `vs_sum_i` input is tied to 0
* `vmxr_i` input is tied to 0
* `vsatp_ppn_i` input is tied to 0
* `vs_asid_i` input is tied to 0
* `hgatp_ppn_i` input is tied to 0
* `vmid_i` input is tied to 0
As EnableAccelerator = 0,::
* `stall_st_pending_i` input is tied to 0
* `acc_valid_i` input is tied to 0
As RVA = False,::
* `amo_valid_commit_i` input is tied to 0
* `amo_req_o` output is tied to 0
* `amo_resp_i` input is tied to 0
As RVF = 0,::
* `fpu_ready_o` output is tied to 0
* `fpu_valid_i` input is tied to 0
* `fpu_fmt_i` input is tied to 0
* `fpu_rm_i` input is tied to 0
* `fpu_frm_i` input is tied to 0
* `fpu_prec_i` input is tied to 0
* `fpu_trans_id_o` output is tied to 0
* `fpu_result_o` output is tied to 0
* `fpu_valid_o` output is tied to 0
* `fpu_exception_o` output is tied to 0
As RVS = False,::
* `enable_translation_i` input is tied to 0
* `en_ld_st_translation_i` input is tied to 0
* `sum_i` input is tied to 0
* `mxr_i` input is tied to 0
* `satp_ppn_i` input is tied to 0
* `asid_i` input is tied to 0
As MMUPresent = 0,::
* `flush_tlb_i` input is tied to 0
As PRIV = MachineOnly,::
* `priv_lvl_i` input is tied to MachineMode
* `ld_st_priv_lvl_i` input is tied to MAchineMode
As PerfCounterEn = 0,::
* `itlb_miss_o` output is tied to 0
* `dtlb_miss_o` output is tied to 0
As IsRVFI = 0,::
* `rvfi_lsu_ctrl_o` output is tied to 0
* `rvfi_mem_paddr_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_frontend_ports]]
.*frontend module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`boot_addr_i` | in | Next PC when reset | SUBSYSTEM | logic[CVA6Cfg.VLEN-1:0]
|`flush_i` | in | Flush requested by FENCE, mis-predict and exception | CONTROLLER | logic
|`halt_i` | in | Halt requested by WFI and Accelerate port | CONTROLLER | logic
|`set_pc_commit_i` | in | Set COMMIT PC as next PC requested by FENCE, CSR side-effect and Accelerate port | CONTROLLER | logic
|`pc_commit_i` | in | COMMIT PC | COMMIT | logic[CVA6Cfg.VLEN-1:0]
|`ex_valid_i` | in | Exception event | COMMIT | logic
|`resolved_branch_i` | in | Mispredict event and next PC | EXECUTE | bp_resolve_t
|`eret_i` | in | Return from exception event | CSR | logic
|`epc_i` | in | Next PC when returning from exception | CSR | logic[CVA6Cfg.VLEN-1:0]
|`trap_vector_base_i` | in | Next PC when jumping into exception | CSR | logic[CVA6Cfg.VLEN-1:0]
|`icache_dreq_o` | out | Handshake between CACHE and FRONTEND (fetch) | CACHES | icache_dreq_t
|`icache_dreq_i` | in | Handshake between CACHE and FRONTEND (fetch) | CACHES | icache_drsp_t
|`fetch_entry_o` | out | Handshake's data between fetch and decode | ID_STAGE | fetch_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`fetch_entry_valid_o` | out | Handshake's valid between fetch and decode | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`fetch_entry_ready_i` | in | Handshake's ready between fetch and decode | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
For any HW configuration,::
* `flush_bp_i` input is tied to 0
As DebugEn = False,::
* `set_debug_pc_i` input is tied to 0
* `debug_mode_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_id_stage_ports]]
.*id_stage module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Fetch flush request | CONTROLLER | logic
|`fetch_entry_i` | in | Handshake's data between fetch and decode | FRONTEND | fetch_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`fetch_entry_valid_i` | in | Handshake's valid between fetch and decode | FRONTEND | logic[CVA6Cfg.NrIssuePorts-1:0]
|`fetch_entry_ready_o` | out | Handshake's ready between fetch and decode | FRONTEND | logic[CVA6Cfg.NrIssuePorts-1:0]
|`issue_entry_o` | out | Handshake's data between decode and issue | ISSUE | scoreboard_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`orig_instr_o` | out | Instruction value | ISSUE | logic[CVA6Cfg.NrIssuePorts-1:0][31:0]
|`issue_entry_valid_o` | out | Handshake's valid between decode and issue | ISSUE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`is_ctrl_flow_o` | out | Report if instruction is a control flow instruction | ISSUE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`issue_instr_ack_i` | in | Handshake's acknowlege between decode and issue | ISSUE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`irq_i` | in | Level sensitive (async) interrupts | SUBSYSTEM | logic[1:0]
|`irq_ctrl_i` | in | Interrupt control status | CSR_REGFILE | irq_ctrl_t
|`hart_id_i` | in | none | none | logic[CVA6Cfg.XLEN-1:0]
|`compressed_ready_i` | in | none | none | logic
|`compressed_resp_i` | in | none | none | x_compressed_resp_t
|`compressed_valid_o` | out | none | none | logic
|`compressed_req_o` | out | none | none | x_compressed_req_t
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As DebugEn = False,::
* `debug_req_i` input is tied to 0
* `debug_mode_i` input is tied to 0
As IsRVFI = 0,::
* `rvfi_is_compressed_o` output is tied to 0
As PRIV = MachineOnly,::
* `priv_lvl_i` input is tied to MachineMode
* `tvm_i` input is tied to 0
* `tw_i` input is tied to 0
* `tsr_i` input is tied to 0
As RVH = False,::
* `v_i` input is tied to 0
* `vfs_i` input is tied to 0
* `vtw_i` input is tied to 0
* `hu_i` input is tied to 0
As RVF = 0,::
* `fs_i` input is tied to 0
* `frm_i` input is tied to 0
As RVV = False,::
* `vs_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_instr_queue_ports]]
.*instr_queue module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Fetch flush request | CONTROLLER | logic
|`instr_i` | in | Instruction | instr_realign | logic[CVA6Cfg.INSTR_PER_FETCH-1:0][31:0]
|`addr_i` | in | Instruction address | instr_realign | logic[CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0]
|`valid_i` | in | Instruction is valid | instr_realign | logic[CVA6Cfg.INSTR_PER_FETCH-1:0]
|`ready_o` | out | Handshake’s ready with CACHE | CACHE | logic
|`consumed_o` | out | Indicates instructions consummed, or popped by ID_STAGE | FRONTEND | logic[CVA6Cfg.INSTR_PER_FETCH-1:0]
|`exception_i` | in | Exception (which is page-table fault) | CACHE | ariane_pkg::frontend_exception_t
|`exception_addr_i` | in | Exception address | CACHE | logic[CVA6Cfg.VLEN-1:0]
|`predict_address_i` | in | Branch predict | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`cf_type_i` | in | Instruction predict address | FRONTEND | ariane_pkg::cf_t[CVA6Cfg.INSTR_PER_FETCH-1:0]
|`replay_o` | out | Replay instruction because one of the FIFO was full | FRONTEND | logic
|`replay_addr_o` | out | Address at which to replay the fetch | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`fetch_entry_o` | out | Handshake’s data with ID_STAGE | ID_STAGE | fetch_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`fetch_entry_valid_o` | out | Handshake’s valid with ID_STAGE | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`fetch_entry_ready_i` | in | Handshake’s ready with ID_STAGE | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVH = False,::
* `exception_gpaddr_i` input is tied to 0
* `exception_tinst_i` input is tied to 0
* `exception_gva_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_instr_realign_ports]]
.*instr_realign module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Fetch flush request | CONTROLLER | logic
|`valid_i` | in | 32-bit block is valid | CACHE | logic
|`serving_unaligned_o` | out | Instruction is unaligned | FRONTEND | logic
|`address_i` | in | 32-bit block address | CACHE | logic[CVA6Cfg.VLEN-1:0]
|`data_i` | in | 32-bit block | CACHE | logic[CVA6Cfg.FETCH_WIDTH-1:0]
|`valid_o` | out | instruction is valid | FRONTEND | logic[CVA6Cfg.INSTR_PER_FETCH-1:0]
|`addr_o` | out | Instruction address | FRONTEND | logic[CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0]
|`instr_o` | out | Instruction | instr_scan&instr_queue | logic[CVA6Cfg.INSTR_PER_FETCH-1:0][31:0]
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_instr_scan_ports]]
.*instr_scan module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`instr_i` | in | Instruction to be predecoded | instr_realign | logic[31:0]
|`rvi_return_o` | out | Return instruction | FRONTEND | logic
|`rvi_call_o` | out | JAL instruction | FRONTEND | logic
|`rvi_branch_o` | out | Branch instruction | FRONTEND | logic
|`rvi_jalr_o` | out | JALR instruction | FRONTEND | logic
|`rvi_jump_o` | out | Unconditional jump instruction | FRONTEND | logic
|`rvi_imm_o` | out | Instruction immediat | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`rvc_branch_o` | out | Branch compressed instruction | FRONTEND | logic
|`rvc_jump_o` | out | Unconditional jump compressed instruction | FRONTEND | logic
|`rvc_jr_o` | out | JR compressed instruction | FRONTEND | logic
|`rvc_return_o` | out | Return compressed instruction | FRONTEND | logic
|`rvc_jalr_o` | out | JALR compressed instruction | FRONTEND | logic
|`rvc_call_o` | out | JAL compressed instruction | FRONTEND | logic
|`rvc_imm_o` | out | Instruction compressed immediat | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_issue_read_operands_ports]]
.*issue_read_operands module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Flush | CONTROLLER | logic
|`issue_instr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | scoreboard_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`orig_instr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0][31:0]
|`issue_instr_valid_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`issue_ack_o` | out | Issue stage acknowledge | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rs1_o` | out | rs1 operand address | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0]
|`rs1_i` | in | rs1 operand | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0]
|`rs1_valid_i` | in | rs1 operand is valid | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rs2_o` | out | rs2 operand address | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0]
|`rs2_i` | in | rs2 operand | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0]
|`rs2_valid_i` | in | rs2 operand is valid | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rs3_o` | out | rs3 operand address | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0]
|`rs3_i` | in | rs3 operand | scoreboard | rs3_len_t[CVA6Cfg.NrIssuePorts-1:0]
|`rs3_valid_i` | in | rs3 operand is valid | scoreboard | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rd_clobber_gpr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | fu_t[2**REG_ADDR_SIZE-1:0]
|`rd_clobber_fpr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | fu_t[2**REG_ADDR_SIZE-1:0]
|`fu_data_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | fu_data_t[CVA6Cfg.NrIssuePorts-1:0]
|`rs1_forwarding_o` | out | Unregistered version of fu_data_o.operanda | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0]
|`rs2_forwarding_o` | out | Unregistered version of fu_data_o.operandb | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0]
|`pc_o` | out | Instruction pc | TO_BE_COMPLETED | logic[CVA6Cfg.VLEN-1:0]
|`is_compressed_instr_o` | out | Is compressed instruction | TO_BE_COMPLETED | logic
|`flu_ready_i` | in | Fixed Latency Unit ready to accept new request | TO_BE_COMPLETED | logic
|`alu_valid_o` | out | ALU output is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`branch_valid_o` | out | Branch instruction is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`branch_predict_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | branchpredict_sbe_t
|`lsu_ready_i` | in | Load Store Unit is ready | TO_BE_COMPLETED | logic
|`lsu_valid_o` | out | Load Store Unit result is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`mult_valid_o` | out | Mult result is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`alu2_valid_o` | out | ALU output is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`csr_valid_o` | out | CSR result is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`cvxif_valid_o` | out | CVXIF result is valid | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`cvxif_ready_i` | in | CVXIF is ready | TO_BE_COMPLETED | logic
|`cvxif_off_instr_o` | out | CVXIF offloaded instruction | TO_BE_COMPLETED | logic[31:0]
|`hart_id_i` | in | CVA6 Hart ID | SUBSYSTEM | logic[CVA6Cfg.XLEN-1:0]
|`x_issue_ready_i` | in | none | none | logic
|`x_issue_resp_i` | in | none | none | x_issue_resp_t
|`x_issue_valid_o` | out | none | none | logic
|`x_issue_req_o` | out | none | none | x_issue_req_t
|`x_register_ready_i` | in | none | none | logic
|`x_register_valid_o` | out | none | none | logic
|`x_register_o` | out | none | none | x_register_t
|`x_commit_valid_o` | out | none | none | logic
|`x_commit_o` | out | none | none | x_commit_t
|`x_transaction_accepted_o` | out | none | none | logic
|`x_transaction_rejected_o` | out | none | none | logic
|`x_issue_writeback_o` | out | none | none | logic
|`x_id_o` | out | none | none | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`waddr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
|`wdata_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0]
|`we_gpr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrCommitPorts-1:0]
|`stall_issue_o` | out | Stall signal, we do not want to fetch any more entries | TO_BE_COMPLETED | logic
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As EnableAccelerator = 0,::
* `stall_i` input is tied to 0
As RVH = False,::
* `tinst_o` output is tied to 0
As RVF = 0,::
* `fpu_ready_i` input is tied to 0
* `fpu_valid_o` output is tied to 0
* `fpu_fmt_o` output is tied to 0
* `fpu_rm_o` output is tied to 0
* `we_fpr_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_issue_stage_ports]]
.*issue_stage module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_unissued_instr_i` | in | TO_BE_COMPLETED | CONTROLLER | logic
|`flush_i` | in | TO_BE_COMPLETED | CONTROLLER | logic
|`decoded_instr_i` | in | Handshake's data with decode stage | ID_STAGE | scoreboard_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`orig_instr_i` | in | instruction value | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0][31:0]
|`decoded_instr_valid_i` | in | Handshake's valid with decode stage | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`is_ctrl_flow_i` | in | Is instruction a control flow instruction | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`decoded_instr_ack_o` | out | Handshake's acknowlege with decode stage | ID_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rs1_forwarding_o` | out | rs1 forwarding | EX_STAGE | [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0]
|`rs2_forwarding_o` | out | rs2 forwarding | EX_STAGE | [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0]
|`fu_data_o` | out | FU data useful to execute instruction | EX_STAGE | fu_data_t[CVA6Cfg.NrIssuePorts-1:0]
|`pc_o` | out | Program Counter | EX_STAGE | logic[CVA6Cfg.VLEN-1:0]
|`is_compressed_instr_o` | out | Is compressed instruction | EX_STAGE | logic
|`flu_ready_i` | in | Fixed Latency Unit is ready | EX_STAGE | logic
|`alu_valid_o` | out | ALU FU is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`resolve_branch_i` | in | Signaling that we resolved the branch | EX_STAGE | logic
|`lsu_ready_i` | in | Load store unit FU is ready | EX_STAGE | logic
|`lsu_valid_o` | out | Load store unit FU is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`branch_valid_o` | out | Branch unit is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`branch_predict_o` | out | Information of branch prediction | EX_STAGE | branchpredict_sbe_t
|`mult_valid_o` | out | Mult FU is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`alu2_valid_o` | out | ALU2 FU is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`csr_valid_o` | out | CSR is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`xfu_valid_o` | out | CVXIF FU is valid | EX_STAGE | logic[CVA6Cfg.NrIssuePorts-1:0]
|`xfu_ready_i` | in | CVXIF is FU ready | EX_STAGE | logic
|`x_off_instr_o` | out | CVXIF offloader instruction value | EX_STAGE | logic[31:0]
|`hart_id_i` | in | CVA6 Hart ID | SUBSYSTEM | logic[CVA6Cfg.XLEN-1:0]
|`x_issue_ready_i` | in | none | none | logic
|`x_issue_resp_i` | in | none | none | x_issue_resp_t
|`x_issue_valid_o` | out | none | none | logic
|`x_issue_req_o` | out | none | none | x_issue_req_t
|`x_register_ready_i` | in | none | none | logic
|`x_register_valid_o` | out | none | none | logic
|`x_register_o` | out | none | none | x_register_t
|`x_commit_valid_o` | out | none | none | logic
|`x_commit_o` | out | none | none | x_commit_t
|`x_transaction_rejected_o` | out | CVXIF Transaction rejected -> instruction is illegal | EX_STAGE | logic
|`trans_id_i` | in | Transaction ID | EX_STAGE | logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0]
|`resolved_branch_i` | in | The branch engine uses the write back from the ALU | EX_STAGE | bp_resolve_t
|`wbdata_i` | in | TO_BE_COMPLETED | EX_STAGE | logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0]
|`ex_ex_i` | in | exception from execute stage or CVXIF | EX_STAGE | exception_t[CVA6Cfg.NrWbPorts-1:0]
|`wt_valid_i` | in | TO_BE_COMPLETED | EX_STAGE | logic[CVA6Cfg.NrWbPorts-1:0]
|`x_we_i` | in | CVXIF write enable | EX_STAGE | logic
|`x_rd_i` | in | CVXIF destination register | ISSUE_STAGE | logic[4:0]
|`waddr_i` | in | TO_BE_COMPLETED | EX_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
|`wdata_i` | in | TO_BE_COMPLETED | EX_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0]
|`we_gpr_i` | in | GPR write enable | EX_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`commit_instr_o` | out | Instructions to commit | COMMIT_STAGE | scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
|`commit_drop_o` | out | Instruction is cancelled | COMMIT_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|`commit_ack_i` | in | Commit acknowledge | COMMIT_STAGE | logic[CVA6Cfg.NrCommitPorts-1:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As PerfCounterEn = 0,::
* `sb_full_o` output is tied to 0
* `stall_issue_o` output is tied to 0
As EnableAccelerator = 0,::
* `stall_i` input is tied to 0
* `issue_instr_o` output is tied to 0
* `issue_instr_hs_o` output is tied to 0
As RVH = False,::
* `tinst_o` output is tied to 0
As RVF = 0,::
* `fpu_ready_i` input is tied to 0
* `fpu_valid_o` output is tied to 0
* `fpu_fmt_o` output is tied to 0
* `fpu_rm_o` output is tied to 0
* `we_fpr_i` input is tied to 0
As IsRVFI = 0,::
* `rvfi_issue_pointer_o` output is tied to 0
* `rvfi_commit_pointer_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_load_store_unit_ports]]
.*load_store_unit module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`stall_st_pending_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`no_st_pending_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`fu_data_i` | in | FU data needed to execute instruction | ISSUE_STAGE | fu_data_t
|`lsu_ready_o` | out | Load Store Unit is ready | ISSUE_STAGE | logic
|`lsu_valid_i` | in | Load Store Unit instruction is valid | ISSUE_STAGE | logic
|`load_trans_id_o` | out | Load transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`load_result_o` | out | Load result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`load_valid_o` | out | Load result is valid | ISSUE_STAGE | logic
|`load_exception_o` | out | Load exception | ISSUE_STAGE | exception_t
|`store_trans_id_o` | out | Store transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`store_result_o` | out | Store result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`store_valid_o` | out | Store result is valid | ISSUE_STAGE | logic
|`store_exception_o` | out | Store exception | ISSUE_STAGE | exception_t
|`commit_i` | in | Commit the first pending store | TO_BE_COMPLETED | logic
|`commit_ready_o` | out | Commit queue is ready to accept another commit request | TO_BE_COMPLETED | logic
|`commit_tran_id_i` | in | Commit transaction ID | TO_BE_COMPLETED | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`icache_areq_i` | in | Instruction cache input request | CACHES | icache_arsp_t
|`icache_areq_o` | out | Instruction cache output request | CACHES | icache_areq_t
|`dcache_req_ports_i` | in | Data cache request output | CACHES | dcache_req_o_t[2:0]
|`dcache_req_ports_o` | out | Data cache request input | CACHES | dcache_req_i_t[2:0]
|`dcache_wbuffer_empty_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`dcache_wbuffer_not_ni_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`pmpcfg_i` | in | PMP configuration | CSR_REGFILE | riscv::pmpcfg_t[CVA6Cfg.NrPMPEntries-1:0]
|`pmpaddr_i` | in | PMP address | CSR_REGFILE | logic[CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVA = False,::
* `amo_valid_commit_i` input is tied to 0
* `amo_req_o` output is tied to 0
* `amo_resp_i` input is tied to 0
As RVH = False,::
* `tinst_i` input is tied to 0
* `enable_g_translation_i` input is tied to 0
* `en_ld_st_g_translation_i` input is tied to 0
* `v_i` input is tied to 0
* `ld_st_v_i` input is tied to 0
* `csr_hs_ld_st_inst_o` output is tied to 0
* `vs_sum_i` input is tied to 0
* `vmxr_i` input is tied to 0
* `vsatp_ppn_i` input is tied to 0
* `vs_asid_i` input is tied to 0
* `hgatp_ppn_i` input is tied to 0
* `vmid_i` input is tied to 0
* `vmid_to_be_flushed_i` input is tied to 0
* `gpaddr_to_be_flushed_i` input is tied to 0
* `flush_tlb_vvma_i` input is tied to 0
* `flush_tlb_gvma_i` input is tied to 0
As RVS = False,::
* `enable_translation_i` input is tied to 0
* `en_ld_st_translation_i` input is tied to 0
* `sum_i` input is tied to 0
* `mxr_i` input is tied to 0
* `satp_ppn_i` input is tied to 0
* `asid_i` input is tied to 0
* `asid_to_be_flushed_i` input is tied to 0
* `vaddr_to_be_flushed_i` input is tied to 0
As PRIV = MachineOnly,::
* `priv_lvl_i` input is tied to MachineMode
* `ld_st_priv_lvl_i` input is tied to MAchineMode
As MMUPresent = 0,::
* `flush_tlb_i` input is tied to 0
As PerfCounterEn = 0,::
* `itlb_miss_o` output is tied to 0
* `dtlb_miss_o` output is tied to 0
As IsRVFI = 0,::
* `rvfi_lsu_ctrl_o` output is tied to 0
* `rvfi_mem_paddr_o` output is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_load_unit_ports]]
.*load_unit module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Flush signal | CONTROLLER | logic
|`valid_i` | in | Load request is valid | LSU_BYPASS | logic
|`lsu_ctrl_i` | in | Load request input | LSU_BYPASS | lsu_ctrl_t
|`pop_ld_o` | out | Pop the load request from the LSU bypass FIFO | LSU_BYPASS | logic
|`valid_o` | out | Load unit result is valid | ISSUE_STAGE | logic
|`trans_id_o` | out | Load transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`result_o` | out | Load result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`ex_o` | out | Load exception | ISSUE_STAGE | exception_t
|`translation_req_o` | out | Request address translation | MMU | logic
|`vaddr_o` | out | Virtual address | MMU | logic[CVA6Cfg.VLEN-1:0]
|`paddr_i` | in | Physical address | MMU | logic[CVA6Cfg.PLEN-1:0]
|`ex_i` | in | Excepted which appears before load | MMU | exception_t
|`page_offset_o` | out | Page offset for address checking | STORE_UNIT | logic[11:0]
|`page_offset_matches_i` | in | Indicates if the page offset matches a store unit entry | STORE_UNIT | logic
|`store_buffer_empty_i` | in | Store buffer is empty | STORE_UNIT | logic
|`commit_tran_id_i` | in | Transaction ID of the committing instruction | COMMIT_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`req_port_i` | in | Data cache request out | CACHES | dcache_req_o_t
|`req_port_o` | out | Data cache request in | CACHES | dcache_req_i_t
|`dcache_wbuffer_not_ni_i` | in | Presence of non-idempotent operations in the D$ write buffer | CACHES | logic
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVH = False,::
* `tinst_o` output is tied to 0
* `hs_ld_st_inst_o` output is tied to 0
* `hlvx_inst_o` output is tied to 0
For any HW configuration,::
* `dtlb_hit_i` input is tied to 1
As MMUPresent = 0,::
* `dtlb_ppn_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_lsu_bypass_ports]]
.*lsu_bypass module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`lsu_req_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | lsu_ctrl_t
|`lsu_req_valid_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`pop_ld_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`pop_st_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`lsu_ctrl_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | lsu_ctrl_t
|`ready_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_mult_ports]]
.*mult module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Flush | CONTROLLER | logic
|`fu_data_i` | in | FU data needed to execute instruction | ISSUE_STAGE | fu_data_t
|`mult_valid_i` | in | Mult instruction is valid | ISSUE_STAGE | logic
|`result_o` | out | Mult result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`mult_valid_o` | out | Mult result is valid | ISSUE_STAGE | logic
|`mult_ready_o` | out | Mutl is ready | ISSUE_STAGE | logic
|`mult_trans_id_o` | out | Mult transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_multiplier_ports]]
.*multiplier module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`trans_id_i` | in | Multiplier transaction ID | Mult | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`mult_valid_i` | in | Multiplier instruction is valid | Mult | logic
|`operation_i` | in | Multiplier operation | Mult | fu_op
|`operand_a_i` | in | A operand | Mult | logic[CVA6Cfg.XLEN-1:0]
|`operand_b_i` | in | B operand | Mult | logic[CVA6Cfg.XLEN-1:0]
|`result_o` | out | Multiplier result | Mult | logic[CVA6Cfg.XLEN-1:0]
|`mult_valid_o` | out | Mutliplier result is valid | Mult | logic
|`mult_ready_o` | out | Multiplier FU is ready | Mult | logic
|`mult_trans_id_o` | out | Multiplier transaction ID | Mult | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|===

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_ras_ports]]
.*ras module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`push_i` | in | Push address in RAS | FRONTEND | logic
|`pop_i` | in | Pop address from RAS | FRONTEND | logic
|`data_i` | in | Data to be pushed | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
|`data_o` | out | Popped data | FRONTEND | ras_t
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
For any HW configuration,::
* `flush_bp_i` input is tied to 0

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////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_scoreboard_ports]]
.*scoreboard module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`sb_full_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`flush_unissued_instr_i` | in | Flush only un-issued instructions | TO_BE_COMPLETED | logic
|`flush_i` | in | Flush whole scoreboard | TO_BE_COMPLETED | logic
|`rd_clobber_gpr_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
|`rd_clobber_fpr_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
|`x_transaction_accepted_i` | in | none | none | logic
|`x_issue_writeback_i` | in | none | none | logic
|`x_id_i` | in | none | none | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`rs1_i` | in | rs1 operand address | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0]
|`rs1_o` | out | rs1 operand | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0]
|`rs1_valid_o` | out | rs1 operand is valid | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rs2_i` | in | rs2 operand address | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0]
|`rs2_o` | out | rs2 operand | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0]
|`rs2_valid_o` | out | rs2 operand is valid | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0]
|`rs3_i` | in | rs3 operand address | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0]
|`rs3_o` | out | rs3 operand | issue_read_operands | rs3_len_t[CVA6Cfg.NrIssuePorts-1:0]
|`rs3_valid_o` | out | rs3 operand is valid | issue_read_operands | logic[CVA6Cfg.NrIssuePorts-1:0]
|`commit_instr_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
|`commit_drop_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrCommitPorts-1:0]
|`commit_ack_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrCommitPorts-1:0]
|`decoded_instr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | scoreboard_entry_t[CVA6Cfg.NrIssuePorts-1:0]
|`orig_instr_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0][31:0]
|`decoded_instr_valid_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`decoded_instr_ack_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`orig_instr_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0][31:0]
|`issue_instr_valid_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`issue_ack_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic[CVA6Cfg.NrIssuePorts-1:0]
|`resolved_branch_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | bp_resolve_t
|`trans_id_i` | in | Transaction ID at which to write the result back | TO_BE_COMPLETED | logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0]
|`wbdata_i` | in | Results to write back | TO_BE_COMPLETED | logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0]
|`ex_i` | in | Exception from a functional unit (e.g.: ld/st exception) | TO_BE_COMPLETED | exception_t[CVA6Cfg.NrWbPorts-1:0]
|`wt_valid_i` | in | Indicates valid results | TO_BE_COMPLETED | logic[CVA6Cfg.NrWbPorts-1:0]
|`x_we_i` | in | Cvxif we for writeback | TO_BE_COMPLETED | logic
|`x_rd_i` | in | CVXIF destination register | ISSUE_STAGE | logic[4:0]
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As EnableAccelerator = 0,::
* `issue_instr_o` output is tied to 0
As IsRVFI = 0,::
* `rvfi_issue_pointer_o` output is tied to 0
* `rvfi_commit_pointer_o` output is tied to 0

44
docs/04_cv32a65x/design/source/port_serdiv.adoc
View file

@ -1,44 +0,0 @@
////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_serdiv_ports]]
.*serdiv module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`id_i` | in | Serdiv translation ID | Mult | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`op_a_i` | in | A operand | Mult | logic[WIDTH-1:0]
|`op_b_i` | in | B operand | Mult | logic[WIDTH-1:0]
|`rem` | in | Serdiv operation | Mult | logic[1:0]opcode_i,//0:udiv,2:urem,1:div,3:
|`in_vld_i` | in | Serdiv instruction is valid | Mult | logic
|`in_rdy_o` | out | Serdiv FU is ready | Mult | logic
|`flush_i` | in | Flush | CONTROLLER | logic
|`out_vld_o` | out | Serdiv result is valid | Mult | logic
|`out_rdy_i` | in | Serdiv is ready | Mult | logic
|`id_o` | out | Serdiv transaction ID | Mult | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`res_o` | out | Serdiv result | Mult | logic[WIDTH-1:0]
|===

78
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@ -1,78 +0,0 @@
////
Copyright 2024 Thales DIS France SAS
Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
You may obtain a copy of the License at https://solderpad.org/licenses/
Original Author: Jean-Roch COULON - Thales
////
[[_CVA6_store_unit_ports]]
.*store_unit module* IO ports
|===
|Signal | IO | Description | connexion | Type
|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
|`flush_i` | in | Flush | CONTROLLER | logic
|`stall_st_pending_i` | in | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`no_st_pending_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`store_buffer_empty_o` | out | Store buffer is empty | TO_BE_COMPLETED | logic
|`valid_i` | in | Store instruction is valid | ISSUE_STAGE | logic
|`lsu_ctrl_i` | in | Data input | ISSUE_STAGE | lsu_ctrl_t
|`pop_st_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`commit_i` | in | Instruction commit | TO_BE_COMPLETED | logic
|`commit_ready_o` | out | TO_BE_COMPLETED | TO_BE_COMPLETED | logic
|`valid_o` | out | Store result is valid | ISSUE_STAGE | logic
|`trans_id_o` | out | Transaction ID | ISSUE_STAGE | logic[CVA6Cfg.TRANS_ID_BITS-1:0]
|`result_o` | out | Store result | ISSUE_STAGE | logic[CVA6Cfg.XLEN-1:0]
|`ex_o` | out | Store exception output | TO_BE_COMPLETED | exception_t
|`translation_req_o` | out | Address translation request | TO_BE_COMPLETED | logic
|`vaddr_o` | out | Virtual address | TO_BE_COMPLETED | logic[CVA6Cfg.VLEN-1:0]
|`paddr_i` | in | Physical address | TO_BE_COMPLETED | logic[CVA6Cfg.PLEN-1:0]
|`ex_i` | in | Exception raised before store | TO_BE_COMPLETED | exception_t
|`page_offset_i` | in | Address to be checked | load_unit | logic[11:0]
|`page_offset_matches_o` | out | Address check result | load_unit | logic
|`req_port_i` | in | Data cache request | CACHES | dcache_req_o_t
|`req_port_o` | out | Data cache response | CACHES | dcache_req_i_t
|===
Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
As RVA = False,::
* `amo_valid_commit_i` input is tied to 0
* `amo_req_o` output is tied to 0
* `amo_resp_i` input is tied to 0
As IsRVFI = 0,::
* `rvfi_mem_paddr_o` output is tied to 0
As RVH = False,::
* `tinst_o` output is tied to 0
* `hs_ld_st_inst_o` output is tied to 0
* `hlvx_inst_o` output is tied to 0
For any HW configuration,::
* `dtlb_hit_i` input is tied to 1

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24
docs/06_cv64a6_mmu/config/config.adoc
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@ -1,24 +0,0 @@
:ohg-config: CV64A6_MMU
:XLEN: 64
:RVA: false
:RVC: true
:RVS: true
:RVU: true
:RVH: false
:SV: SV0
:RVZicfilp: false
:RVZicfiss: false
:RVZpm: false
:RVZsmstateen: false
:RVZsmcsrind-RVZsscsrind: false
:RVZsmepmp: false
:RVZsmcntrpmf: false
:RVZsmrnmi: false
:RVZsmcdeleg: false
:RVZsstc: false
:RVZsscofpmf: false
:RVZsmmpm: false
:DCacheEn: false
:MTvalEn: false
:MTvecDirectEn: true
:note: false

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24
docs/Makefile
View file

@ -1,20 +1,12 @@
# Minimal makefile for Sphinx documentation
#
all: prepare sphinx
# You can set these variables from the command line, and also
# from the environment for the first two.
SPHINXOPTS ?=
SPHINXBUILD ?= sphinx-build
SOURCEDIR = .
BUILDDIR = _build
prepare:
make -C 04_cv32a65x/riscv priv-html unpriv-html
make -C 04_cv32a65x/design design-html
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
make -C 06_cv64a6_mmu/riscv priv-html unpriv-html
.PHONY: help Makefile
sphinx:
sphinx-build . _build
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: all prepare sphinx

14
docs/README.md
View file

@ -1,26 +1,26 @@
# CVA6 documentation
CVA6 documentation is published as a Read the Docs documentation.
It can be generated by running `make html` in this directory.
It can be generated by running `make` in this directory.
This generates all necessary sub-documents.
## Configuration-specific manuals
For each supported target (e.g. `cv32a65x`), there are two manuals included in the main documentation: a tailored RISC-V instruction set manual, and a design documentation.
These documents are generated as HTML files, are committed to the repository, and are included when generating the main documentation.
These documents are generated when building the main documentation.
### Instruction set manual
Instruction set manuals (privileged & unprivileged) are based on the official RISC-V Instruction Set Manual repository.
Some parts are stripped down or annotated to only include what's relevant for each specific configuration.
These manuals can be generated with: `make -C 04_cv32a65x/riscv priv-html unpriv-html`.
These manuals can be manually generated with: `make -C 04_cv32a65x/riscv priv-html unpriv-html`.
Replace `04_cv32a65x` with the desired target.
Some of the files used in this documentation (`config.adoc`) are directly generated from the RTL.
### Design documentation
Design documentation describes the internal architecture of the CVA6 processor.
It can be generated with: `make -C 04_cv32a65x/design design-html`.
Some of the files used in this documentation (`port_*.adoc`) are directly generated from the RTL.
They can be updated by running `python3 scripts/spec_builder.py`.
It can be manually generated with: `make -C 04_cv32a65x/design design-html`.
Some of the files used in this documentation (`config.adoc`, `parameters.adoc`, `port_*.adoc`, `csr.adoc`, `isa.adoc`) are directly generated from the RTL.

16
docs/design/build.mk
View file

@ -10,6 +10,8 @@ ifeq ($(CONFIG),)
$(error CONFIG must be defined)
endif
current_dir = $(shell pwd)
# Path of current file, intended to be included by a configuration subfolder
design_dir := $(dir $(lastword $(MAKEFILE_LIST)))
@ -17,14 +19,18 @@ all: design-pdf design-html
setup:
mkdir -p build
pwd
echo $(design_dir)
cp -r $(design_dir)/design-manual/* build
cp -r $(design_dir)/../../config/gen_from_riscv_config/$(CONFIG)/* build/source
cp -r $(design_dir)/../riscv-isa/riscv-isa-manual/docs-resources build
cp ../config/config.adoc build/source
cp $(design_dir)/../common/*.adoc build/source
cp -rf source build
cp -rf source/* build/source
cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/$(CONFIG)/isa_updater.yaml -t $(CONFIG) -f adoc
cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml -c ../riscv-config/$(CONFIG)/generated/custom_gen.yaml -m updaters/$(CONFIG)/csr_updater.yaml -t $(CONFIG) -f adoc
cp -r $(design_dir)/../../config/gen_from_riscv_config/$(CONFIG)/* build/source
cd ../.. && python3 scripts/spec_builder.py --target $(CONFIG) --gen-config $(current_dir)/build/source/config.adoc --gen-parameters $(current_dir)/build/source/parameters.adoc --gen-ports $(current_dir)/build/source
design-pdf: setup
cd build; make SKIP_DOCKER=true build/design.pdf

4
docs/design/design-manual/source/architecture.adoc
View file

@ -24,10 +24,10 @@ Connections between modules are illustrated in the following block diagram. FRON
image:{ohg-config}_subsystems.png[{ohg-config} pipeline and modules]
include::cv32a6_frontend.adoc[]
include::cva6_frontend.adoc[]
include::cva6_id_stage.adoc[]
include::cva6_issue_stage.adoc[]
include::cv32a6_execute.adoc[]
include::cva6_execute.adoc[]
include::cva6_commit_stage.adoc[]
include::cva6_controller.adoc[]
include::cva6_csr_regfile.adoc[]

13
docs/design/design-manual/source/cva6_frontend.adoc
View file

@ -163,11 +163,12 @@ These outputs are used by the branch prediction feature.
include::port_instr_scan.adoc[]
ifeval::[{BHTEntries} > 0]
[[bht-branch-history-table-submodule]]
BHT (Branch History Table) submodule
++++++++++++++++++++++++++++++++++++
BHT is implemented as a memory which is composed of **BHTDepth configuration parameter** entries. The lower address bits of the virtual address point to the memory entry.
BHT is implemented as a memory which is composed of {BHTEntries} entries. The lower address bits of the virtual address point to the memory entry.
When a branch instruction is resolved by the EX_STAGE module, the branch PC and the taken (or not taken) status information is stored in the Branch History Table.
@ -185,14 +186,15 @@ When a branch instruction is pre-decoded by instr_scan submodule, the BHT valids
The BHT is never flushed.
include::port_bht.adoc[]
endif::[]
ifeval::[{BTBEntries} > 0]
[[btb-branch-target-buffer-submodule]]
BTB (Branch Target Buffer) submodule
++++++++++++++++++++++++++++++++++++
BTB is implemented as an array which is composed of **BTBDepth configuration parameter** entries.
BTB is implemented as an array which is composed of {BTBEntries} entries.
The lower address bits of the virtual address point to the memory entry.
When an JALR instruction is found mispredicted by the EX_STAGE module, the JALR PC and the target address are stored into the BTB.
@ -207,12 +209,14 @@ In this case, the BTB provides the predicted target address.
The BTB is never flushed.
include::port_btb.adoc[]
endif::[]
ifeval::[{RASDepth} > 0]
[[ras-return-address-stack-submodule]]
RAS (Return Address Stack) submodule
++++++++++++++++++++++++++++++++++++
RAS is implemented as a LIFO which is composed of **RASDepth configuration parameter** entries.
RAS is implemented as a LIFO which is composed of {RASDepth} entries.
When a JAL instruction is pre-decoded by the instr_scan, the PC of the instruction following JAL instruction is pushed into the RAS when the JAL instruction is added to the instruction queue.
@ -222,3 +226,4 @@ If the predicted return address is wrong due for instance to speculation or RAS
The RAS is never flushed.
include::port_ras.adoc[]
endif::[]

2
docs/design/design-manual/source/design.adoc
View file

@ -37,4 +37,4 @@ include::intro.adoc[]
include::subsystem.adoc[]
include::functionality.adoc[]
include::architecture.adoc[]
include::cv32a6_glossary.adoc[]
include::glossary.adoc[]

2
docs/design/design-manual/source/intro.adoc
View file

@ -74,7 +74,7 @@ https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/.
University,
https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf.
CV32A6 is a standards-compliant 32-bit processor fully compliant with
{ohg-config} is a standards-compliant {XLEN}-bit processor fully compliant with
RISC-V specifications: [RVunpriv], [RVpriv] and [RVdbg] and passes
[RVcompat] compatibility tests, as requested by [GEN-10] in [CVA6req].

12
docs/design/design-manual/source/mmu.adoc
View file

@ -622,7 +622,7 @@ shows the entry selection for replacement.
|*Path Traverse* |*PLRU Bits* |*Entry to replace*
a|
0 -> 1 -> 3::
*
*
a|
___
@ -642,7 +642,7 @@ _
a|
0 -> 1 -> 4::
*
*
a|
___
@ -662,7 +662,7 @@ _
a|
0 -> 2 -> 5::
*
*
a|
___
@ -682,7 +682,7 @@ _
a|
0 -> 2 -> 6::
*
*
a|
___
@ -931,7 +931,7 @@ Page Table Walker
-----------------
The "CVA6 Page Table Walker (PTW) for MMU Sv32" is a hardware module
developed for the CV32A6 processor architecture, designed to facilitate
developed for the CVA6 processor architecture, designed to facilitate
the translation of virtual addresses into physical addresses, a crucial
task in memory access management.
@ -946,7 +946,7 @@ Key features of this PTW module include support for two levels of page
tables (LVL1 and LVL2) in the Sv32 standard, accommodating instruction
and data page table walks. It rigorously validates and verifies page
table entries (PTEs) to ensure translation accuracy and adherence to
access permissions. This module seamlessly integrates with the CV32A6
access permissions. This module seamlessly integrates with the CVA6
processor's memory management unit (MMU), which governs memory access
control. It also takes into account global mapping, access flags, and
privilege levels during the translation process, ensuring that memory

35
docs/make.bat
View file

@ -1,35 +0,0 @@
@ECHO OFF
pushd %~dp0
REM Command file for Sphinx documentation
if "%SPHINXBUILD%" == "" (
set SPHINXBUILD=sphinx-build
)
set SOURCEDIR=.
set BUILDDIR=_build
if "%1" == "" goto help
%SPHINXBUILD% >NUL 2>NUL
if errorlevel 9009 (
echo.
echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
echo.installed, then set the SPHINXBUILD environment variable to point
echo.to the full path of the 'sphinx-build' executable. Alternatively you
echo.may add the Sphinx directory to PATH.
echo.
echo.If you don't have Sphinx installed, grab it from
echo.http://sphinx-doc.org/
exit /b 1
)
%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
goto end
:help
%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
:end
popd

8
docs/riscv-isa/build.mk
View file

@ -10,6 +10,8 @@ ifeq ($(CONFIG),)
$(error CONFIG must be defined)
endif
current_dir = $(shell pwd)
# Path of current file, intended to be included by a configuration subfolder
riscv-isa_dir := $(dir $(lastword $(MAKEFILE_LIST)))
@ -17,10 +19,12 @@ all: priv-pdf priv-html unpriv-pdf unpriv-html
setup:
mkdir -p build/riscv-isa-manual
cp -r $(riscv-isa_dir)/riscv-isa-manual/* build/riscv-isa-manual
cp -r $(riscv-isa_dir)/src build/riscv-isa-manual
cp -r $(riscv-isa_dir)/../common/*.adoc build/riscv-isa-manual/src
cp ../config/config.adoc build/riscv-isa-manual/src
cp $(riscv-isa_dir)/../common/*.adoc build/riscv-isa-manual/src
cd ../.. && python3 scripts/spec_builder.py --target $(CONFIG) --gen-config $(current_dir)/build/riscv-isa-manual/src/config.adoc
priv-pdf: setup
cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.pdf

2
docs/scripts/parameters_extractor.py
View file

@ -19,7 +19,7 @@ from classes import Parameter
sys.path.append(os.getcwd() + "/../util")
from user_config import get_config
def parameters_extractor(spec_number, target):
def parameters_extractor(target):
parameters = {}
file_in = "../core/include/config_pkg.sv"

247
docs/scripts/spec_builder.py
View file

@ -11,6 +11,7 @@
import re
import sys
import os
from classes import Parameter
from classes import PortIO
@ -44,6 +45,31 @@ HEADER_ADOC = """\
"""
DEFAULT_PARAMS = {
'RVE': False,
'RVQ': False,
'RVZabha': False,
'RVZacas': False,
'RVZawrs': False,
'RVZfa': False,
'RVZfbf-RZvfbf': False,
'RVZfh': False,
'RVZfinx': False,
'RVZicbo': False,
'RVZicfilp': False,
'RVZpm': False,
'RVZsmepmp': False,
'RVZsmmpm': False,
'RVZsmrnmi': False,
'RVZsmstateen': False,
'RVZsscofpmf': False,
'RVZssdbltrp': False,
'RVZsstc': False,
'RVZtso': False,
'RVZvk': False,
'SV': 'SV0'
}
def print_to_rst(pathout, target, module, ports, comments):
fileout = f"{pathout}/port_{module}.rst"
print("Output file " + fileout)
@ -107,131 +133,144 @@ def print_to_adoc(pathout, target, module, ports, comments):
fout.write(f"{comment[0]},::\n* {comment[1]}\n")
fout.write("\n")
def main():
PATH = "04_cv32a65x"
generate_file_type = "adoc"
[spec_number, target] = PATH.split("_")
print(spec_number, target)
# Parameters
parameters = parameters_extractor(spec_number, target)
pathout = f"./{spec_number}_{target}/design/source"
if generate_file_type in ['rst']:
fileout = f"{pathout}/parameters_{target}.rst"
writeout_parameter_table(fileout, parameters, target)
elif generate_file_type in ['adoc']:
pathout = f"./{spec_number}_{target}/design/source"
fileout = f"{pathout}/parameters.adoc"
writeout_parameter_table_adoc(fileout, parameters, target)
def _format_parameter_adoc(name, value):
if type(value) is bool:
ret = str(value).lower()
else:
raise Exception("Format de sortie %s non pris en charge"%generate_file_type)
ret = str(value)
return f":{name}: {ret}\n"
def main():
import argparse
parser = argparse.ArgumentParser()
parser.add_argument("--target", required=True)
parser.add_argument("--gen-config", help="Generate target variables documentation file")
parser.add_argument("--gen-parameters", help="Generate target parameters files")
parser.add_argument("--gen-ports-folder", help="Generate target ports files")
args = parser.parse_args()
target = args.target
parameters = parameters_extractor(target)
# User_cfg
export_user_cfg_doc("01_cva6_user/user_cfg_doc.rst", parameters)
# Parameters
if args.gen_parameters is not None:
os.makedirs(os.path.dirname(args.gen_parameters), exist_ok=True)
writeout_parameter_table_adoc(args.gen_parameters, parameters, target)
print(f"File {args.gen_parameters} written")
# Config
if args.gen_config is not None:
os.makedirs(os.path.dirname(args.gen_config), exist_ok=True)
with open(args.gen_config, "w") as fout:
fout.write(f":ohg-config: {target.upper()}\n")
for name, value in DEFAULT_PARAMS.items():
fout.write(_format_parameter_adoc(name, value))
for name, parameter in parameters.items():
fout.write(_format_parameter_adoc(name, parameter.value))
print(f"File {args.gen_config} written")
# Ports
file = []
file.append("../core/cva6.sv")
file.append("../core/frontend/frontend.sv")
file.append("../core/frontend/bht.sv")
file.append("../core/frontend/btb.sv")
file.append("../core/frontend/ras.sv")
file.append("../core/frontend/instr_queue.sv")
file.append("../core/frontend/instr_scan.sv")
file.append("../core/instr_realign.sv")
file.append("../core/id_stage.sv")
file.append("../core/issue_stage.sv")
file.append("../core/ex_stage.sv")
file.append("../core/commit_stage.sv")
file.append("../core/controller.sv")
file.append("../core/csr_regfile.sv")
file.append("../core/decoder.sv")
file.append("../core/compressed_decoder.sv")
file.append("../core/scoreboard.sv")
file.append("../core/issue_read_operands.sv")
file.append("../core/alu.sv")
file.append("../core/branch_unit.sv")
file.append("../core/csr_buffer.sv")
file.append("../core/mult.sv")
file.append("../core/multiplier.sv")
file.append("../core/serdiv.sv")
file.append("../core/load_store_unit.sv")
file.append("../core/load_unit.sv")
file.append("../core/store_unit.sv")
file.append("../core/lsu_bypass.sv")
file.append("../core/cvxif_fu.sv")
file.append("../core/cache_subsystem/cva6_hpdcache_subsystem.sv")
if args.gen_ports_folder is not None:
file = []
file.append("../core/cva6.sv")
file.append("../core/frontend/frontend.sv")
file.append("../core/frontend/bht.sv")
file.append("../core/frontend/btb.sv")
file.append("../core/frontend/ras.sv")
file.append("../core/frontend/instr_queue.sv")
file.append("../core/frontend/instr_scan.sv")
file.append("../core/instr_realign.sv")
file.append("../core/id_stage.sv")
file.append("../core/issue_stage.sv")
file.append("../core/ex_stage.sv")
file.append("../core/commit_stage.sv")
file.append("../core/controller.sv")
file.append("../core/csr_regfile.sv")
file.append("../core/decoder.sv")
file.append("../core/compressed_decoder.sv")
file.append("../core/scoreboard.sv")
file.append("../core/issue_read_operands.sv")
file.append("../core/alu.sv")
file.append("../core/branch_unit.sv")
file.append("../core/csr_buffer.sv")
file.append("../core/mult.sv")
file.append("../core/multiplier.sv")
file.append("../core/serdiv.sv")
file.append("../core/load_store_unit.sv")
file.append("../core/load_unit.sv")
file.append("../core/store_unit.sv")
file.append("../core/lsu_bypass.sv")
file.append("../core/cvxif_fu.sv")
file.append("../core/cache_subsystem/cva6_hpdcache_subsystem.sv")
black_list = define_blacklist(parameters)
black_list = define_blacklist(parameters)
for filein in file:
comments = []
a = re.match(r".*\/(.*).sv", filein)
module = a.group(1)
print("Input file " + filein)
ports = []
with open(filein, "r", encoding="utf-8") as fin:
description = "none"
connexion = "none"
for line in fin:
e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line)
d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
if d:
description = d.group(1)
connexion = d.group(2)
if e:
name = e.group(3)
name = name.replace(",", "")
data_type = e.group(2)
data_type = data_type.replace(" ", "")
if connexion in black_list:
for i, comment in enumerate(comments):
if black_list[connexion][0] == comment[0]:
comment[1] = (
comment[1]
+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}"
)
break
else:
comments.append(
[
black_list[connexion][0],
f"``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}",
]
)
else:
if name in black_list:
for filein in file:
comments = []
a = re.match(r".*\/(.*).sv", filein)
module = a.group(1)
print("Input file " + filein)
ports = []
with open(filein, "r", encoding="utf-8") as fin:
description = "none"
connexion = "none"
for line in fin:
e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line)
d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
if d:
description = d.group(1)
connexion = d.group(2)
if e:
name = e.group(3)
name = name.replace(",", "")
data_type = e.group(2)
data_type = data_type.replace(" ", "")
if connexion in black_list:
for i, comment in enumerate(comments):
if black_list[name][0] == comment[0]:
if black_list[connexion][0] == comment[0]:
comment[1] = (
comment[1]
+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[name][1]}"
+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}"
)
break
else:
comments.append(
[
black_list[name][0],
f"``{name}`` {e.group(1)}put is tied to {black_list[name][1]}",
black_list[connexion][0],
f"``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}",
]
)
else:
ports.append(
PortIO(
name, e.group(1), data_type, description, connexion
if name in black_list:
for i, comment in enumerate(comments):
if black_list[name][0] == comment[0]:
comment[1] = (
comment[1]
+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[name][1]}"
)
break
else:
comments.append(
[
black_list[name][0],
f"``{name}`` {e.group(1)}put is tied to {black_list[name][1]}",
]
)
else:
ports.append(
PortIO(
name, e.group(1), data_type, description, connexion
)
)
)
description = "none"
connexion = "none"
description = "none"
connexion = "none"
if generate_file_type in ['rst']:
print_to_rst(pathout, target, module, ports, comments)
elif generate_file_type in ['adoc']:
print_to_adoc(pathout, target, module, ports, comments)
else:
raise Exception("Format de sortie %s non pris en charge"%generate_file_type)
print_to_adoc(args.gen_ports_folder, target, module, ports, comments)
def export_user_cfg_doc(out_path, params):
with open(out_path, "w", encoding="utf-8") as f: