mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-23 13:47:13 -04:00
75 lines
1.9 KiB
Bash
75 lines
1.9 KiB
Bash
# Copyright 2024 CoreLab Tech
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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noprint=""
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if [ "$1" == "--no-print" ]; then
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noprint="-DHAS_PRINTF=0"
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fi
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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source ./verif/sim/setup-env.sh
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DV_SIMULATORS=vcs-uvm
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+UVM_VERBOSITY=$UVM_VERBOSITY"
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export DV_OPTS="$DV_OPTS --issrun_opts=+mem_vp_enabled=1"
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make clean
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make -C verif/sim clean_all
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cd verif/sim/
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src0=../tests/custom/debug_test/debug_test.c
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srcA=(
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../tests/custom/debug_test/debugger_exception.S
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../tests/custom/debug_test/debugger.S
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../tests/custom/debug_test/handlers.S
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../tests/custom/debug_test/single_step.S
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../tests/custom/debug_test/trigger_code.S
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../tests/custom/debug_test/bsp/crt0.S
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../tests/custom/debug_test/bsp/syscalls.c
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../tests/custom/debug_test/bsp/vectors.S
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)
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cflags_opt=(
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-mabi=ilp32 \
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-march=rv32imac_zicsr_zifencei \
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-Os -g -static -Wall -pedantic \
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-nostartfiles \
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-Wunused-variable \
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-mno-relax
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)
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cflags=(
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"${cflags_opt[@]}"
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"-DCOMPILER_FLAGS='\"${cflags_opt[*]}\"'"
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-I../tests/custom/debug_test/
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-I../tests/custom/debug_test/bsp
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)
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default_target="cv32a6_imac_sv0"
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link_ld="../tests/custom/debug_test/bsp/link.ld"
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set -x
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python3 cva6.py \
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--target "$default_target" \
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--iss="$DV_SIMULATORS" \
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--iss_yaml=cva6.yaml \
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--c_tests "$src0" \
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--gcc_opts "${srcA[*]} ${cflags[*]}" \
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--linker "$link_ld" \
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$DV_OPTS -v
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