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https://github.com/openhwgroup/cva6.git
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160 lines
3.9 KiB
ArmAsm
160 lines
3.9 KiB
ArmAsm
#Copyright 202[x] Silicon Labs, Inc.
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#
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#This file, and derivatives thereof are licensed under the
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#Solderpad License, Version 2.0 (the "License");
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#Use of this file means you agree to the terms and conditions
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#of the license and are in full compliance with the License.
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#You may obtain a copy of the License at
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#
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# https://solderpad.org/licenses/SHL-2.0/
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#
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#Unless required by applicable law or agreed to in writing, software
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#and hardware implementations thereof
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#distributed under the License is distributed on an "AS IS" BASIS,
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#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED.
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#See the License for the specific language governing permissions and
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#limitations under the License.
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#include "corev_uvmt.h"
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.section .trigger_code_sect, "ax"
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.set test_ret_val, CV_VP_STATUS_FLAGS_BASE
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.set test_fail, 0x1
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.global _trigger_exit
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.global _trigger_test
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.global _trigger_code
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.global _trigger_test_ebreak
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.global _trigger_code_ebreak
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.global _trigger_code_illegal_insn
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.global _trigger_code_branch_insn
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.global _trigger_code_multicycle_insn
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.global _trigger_code_cebreak
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.type _trigger_code, @function
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.type _trigger_code_ebreak, @function
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.type _trigger_code_cebreak, @function
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.type _trigger_code_illegal_insn, @function
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.type _trigger_code_branch_insn, @function
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.type _trigger_code_multicycle_insn, @function
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_trigger_code_ebreak:
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.4byte 0x00100073
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ret
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_trigger_code_cebreak:
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c.ebreak
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ret
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_trigger_code_illegal_insn:
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dret
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ret
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_trigger_code_branch_insn:
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beq t0, t1, __trigger_fail
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ret
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_trigger_code_multicycle_insn:
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mulhsu t0, t0, t1
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ret
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_trigger_test_ebreak:
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addi sp,sp,-30
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sw t0, 0(sp)
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sw t1, 4(sp)
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sw a0, 8(sp)
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sw a1, 12(sp)
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sw a2, 16(sp)
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sw ra, 20(sp)
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# a0 holds argument
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# 0 - ebreak
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# 1 - c.c.ebreak
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# 2 - illegal instruction
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# 3 - branch instruction
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# 4 - multicycle instruction (mulhsu)
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mv t1, a0
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li t0, 0
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beq t0, t1, _jmp_ebreak
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li t0, 1
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beq t0, t1, _jmp_cebreak
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li t0, 2
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beq t0, t1, _jmp_illegal_insn
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li t0, 3
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beq t0, t1, _jmp_branch_insn
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li t0, 4
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beq t0, t1, _jmp_multicycle_insn
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_jmp_ebreak:
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jal ra, _trigger_code_ebreak
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j __trigger_done
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_jmp_cebreak:
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jal ra, _trigger_code_cebreak
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j __trigger_done
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_jmp_illegal_insn:
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jal ra, _trigger_code_illegal_insn
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j __trigger_done
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_jmp_branch_insn:
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jal ra, _trigger_code_branch_insn
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j __trigger_done
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_jmp_multicycle_insn:
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jal ra, _trigger_code_multicycle_insn
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j __trigger_done
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# j __trigger_done
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// We will trigger on the _trigger_code addess
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// We should not expect the first instruction to execute
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// The debugger code will move the PC to the trigger_exit_code
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// Which essentially avoid executing all of the code in the trigger_code
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_trigger_code:
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add a2,a0,a1
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ret
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_trigger_exit:
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ret
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_trigger_test:
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addi sp,sp,-30
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sw t0, 0(sp)
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sw t1, 4(sp)
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sw a0, 8(sp)
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sw a1, 12(sp)
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sw a2, 16(sp)
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sw ra, 20(sp)
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// a0 holds input to function (expect trigger)
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mv t1, a0
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// Load up some random data to add
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li a0, 7893
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li a1, 1452
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li a2, 191 // a2 value will be overwrriten by _trigger_code
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mv t2, a2 // keep a copy of the value to compare against
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// Call function that will have a trigger match
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// If no trigger match, then a2=a0+a1
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// Else if trigger matched, then a2 is not modified
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jal ra, _trigger_code
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// if (expect trigger) check against original value (in t2)
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bne t1 ,x0, __trigger_check
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// else
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// trigger match not expected, function executes as normal
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// set execpted value to t2 = a0 + a1
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add t2, a0, a1
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__trigger_check:
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beq t2,a2,__trigger_done
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__trigger_fail:
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li a0, CV_VP_STATUS_FLAGS_BASE
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li t0, 1
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sw t0, 0(a0)
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__trigger_done:
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lw t0, 0(sp)
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lw t1, 4(sp)
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lw a0, 8(sp)
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lw a1, 12(sp)
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lw a2, 16(sp)
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lw ra, 20(sp)
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addi sp,sp,30
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ret
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