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cva6/corev_apu
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André Sintzoff fd8e971f1e
Clean-up flists (#750) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2021-10-09 10:17:39 +02:00
..
axi@3f5d5b540a Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
axi_mem_if@4650ca9006 Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
axi_node@a29a69a543 Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
bootrom Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
clint Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
fpga Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
fpga-support@a3ba269c0f Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
include Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
openpiton Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
register_interface@d8aeccc65f Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
riscv-dbg@e19d69efe7 riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug (#746) 2021-10-01 17:02:34 +02:00
rv_plic@ebe3e98889 Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
src Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
tb Clean-up flists (#750) 2021-10-09 10:17:39 +02:00