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4619a67fc6
Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv. Also reorders port maps to keep the same order as port declarations.
261 lines
8.9 KiB
Systemverilog
261 lines
8.9 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 08.05.2017
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// Description: Flush controller
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module controller
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import ariane_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter type bp_resolve_t = logic
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) (
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// Subsystem Clock - SUBSYSTEM
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input logic clk_i,
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// Asynchronous reset active low - SUBSYSTEM
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input logic rst_ni,
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// Virtualization mode - CSR_REGFILE
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input logic v_i,
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// Set PC om PC Gen - FRONTEND
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output logic set_pc_commit_o,
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// Flush the IF stage - FRONTEND
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output logic flush_if_o,
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// Flush un-issued instructions of the scoreboard - FRONTEND
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output logic flush_unissued_instr_o,
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// Flush ID stage - ID_STAGE
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output logic flush_id_o,
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// Flush EX stage - EX_STAGE
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output logic flush_ex_o,
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// Flush branch predictors - FRONTEND
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output logic flush_bp_o,
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// Flush ICache - CACHE
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output logic flush_icache_o,
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// Flush DCache - CACHE
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output logic flush_dcache_o,
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// Acknowledge the whole DCache Flush - CACHE
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input logic flush_dcache_ack_i,
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// Flush TLBs - EX_STAGE
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output logic flush_tlb_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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output logic flush_tlb_vvma_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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output logic flush_tlb_gvma_o,
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// Halt request from CSR (WFI instruction) - CSR_REGFILE
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input logic halt_csr_i,
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// Halt request from accelerator dispatcher - ACC_DISPATCHER
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input logic halt_acc_i,
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// Halt signal to commit stage - COMMIT_STAGE
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output logic halt_o,
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// Return from exception - CSR_REGFILE
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input logic eret_i,
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// We got an exception, flush the pipeline - FRONTEND
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input logic ex_valid_i,
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// set the debug pc from CSR - FRONTEND
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input logic set_debug_pc_i,
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// We got a resolved branch, check if we need to flush the front-end - EX_STAGE
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input bp_resolve_t resolved_branch_i,
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// We got an instruction which altered the CSR, flush the pipeline - CSR_REGFILE
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input logic flush_csr_i,
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// fence.i in - ACC_DISPATCH
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input logic fence_i_i,
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// fence in - ACC_DISPATCH
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input logic fence_i,
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// We got an instruction to flush the TLBs and pipeline - COMMIT_STAGE
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input logic sfence_vma_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic hfence_vvma_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic hfence_gvma_i,
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// Flush request from commit stage - COMMIT_STAGE
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input logic flush_commit_i,
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// Flush request from accelerator - ACC_DISPATCHER
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input logic flush_acc_i
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);
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// active fence - high if we are currently flushing the dcache
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logic fence_active_d, fence_active_q;
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logic flush_dcache;
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// ------------
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// Flush CTRL
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// ------------
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always_comb begin : flush_ctrl
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fence_active_d = fence_active_q;
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set_pc_commit_o = 1'b0;
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flush_if_o = 1'b0;
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flush_unissued_instr_o = 1'b0;
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flush_id_o = 1'b0;
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flush_ex_o = 1'b0;
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flush_dcache = 1'b0;
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flush_icache_o = 1'b0;
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flush_tlb_o = 1'b0;
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flush_tlb_vvma_o = 1'b0;
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flush_tlb_gvma_o = 1'b0;
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flush_bp_o = 1'b0;
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// ------------
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// Mis-predict
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// ------------
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// flush on mispredict
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if (resolved_branch_i.is_mispredict) begin
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// flush only un-issued instructions
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flush_unissued_instr_o = 1'b1;
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// and if stage
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flush_if_o = 1'b1;
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end
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// ---------------------------------
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// FENCE
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// ---------------------------------
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if (fence_i) begin
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// this can be seen as a CSR instruction with side-effect
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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// this is not needed in the case since we
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// have a write-through cache in this case
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if (CVA6Cfg.DCacheType == config_pkg::WB) begin
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flush_dcache = 1'b1;
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fence_active_d = 1'b1;
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end
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end
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// ---------------------------------
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// FENCE.I
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// ---------------------------------
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if (fence_i_i) begin
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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flush_icache_o = 1'b1;
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// this is not needed in the case since we
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// have a write-through cache in this case
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if (CVA6Cfg.DCacheType == config_pkg::WB) begin
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flush_dcache = 1'b1;
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fence_active_d = 1'b1;
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end
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end
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// this is not needed in the case since we
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// have a write-through cache in this case
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if (CVA6Cfg.DCacheType == config_pkg::WB) begin
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// wait for the acknowledge here
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if (flush_dcache_ack_i && fence_active_q) begin
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fence_active_d = 1'b0;
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// keep the flush dcache signal high as long as we didn't get the acknowledge from the cache
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end else if (fence_active_q) begin
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flush_dcache = 1'b1;
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end
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end
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// ---------------------------------
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// SFENCE.VMA
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// ---------------------------------
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if (CVA6Cfg.RVS && sfence_vma_i) begin
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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if (CVA6Cfg.RVH && v_i) flush_tlb_vvma_o = 1'b1;
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else flush_tlb_o = 1'b1;
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end
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// ---------------------------------
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// HFENCE.VVMA
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// ---------------------------------
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if (CVA6Cfg.RVH && hfence_vvma_i) begin
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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flush_tlb_vvma_o = 1'b1;
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end
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// ---------------------------------
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// HFENCE.GVMA
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// ---------------------------------
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if (CVA6Cfg.RVH && hfence_gvma_i) begin
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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flush_tlb_gvma_o = 1'b1;
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end
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// ---------------------------------
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// CSR side effects and accelerate port
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// ---------------------------------
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// Set PC to commit stage and flush pipeline
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if (flush_csr_i || flush_acc_i) begin
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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end else if (CVA6Cfg.RVA && flush_commit_i) begin
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set_pc_commit_o = 1'b1;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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end
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// ---------------------------------
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// 1. Exception
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// 2. Return from exception
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// ---------------------------------
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if (ex_valid_i || eret_i || (CVA6Cfg.DebugEn && set_debug_pc_i)) begin
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// don't flush pcgen as we want to take the exception: Flush PCGen is not a flush signal
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// for the PC Gen stage but instead tells it to take the PC we gave it
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set_pc_commit_o = 1'b0;
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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// this potentially reduces performance, but is needed
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// to suppress speculative fetches to virtual memory from
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// machine mode. TODO: remove when PMA checkers have been
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// added to the system
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flush_bp_o = 1'b1;
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end
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end
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// ----------------------
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// Halt Logic
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// ----------------------
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always_comb begin
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// halt the core if the fence is active
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halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DCacheType == config_pkg::WB && fence_active_q);
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end
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// ----------------------
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// Registers
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// ----------------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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fence_active_q <= 1'b0;
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flush_dcache_o <= 1'b0;
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end else begin
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fence_active_q <= fence_active_d;
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// register on the flush signal, this signal might be critical
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flush_dcache_o <= flush_dcache;
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end
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end
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endmodule
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