cva6/corev_apu/fpga/scripts/program.tcl
André Sintzoff 3ddf797e95
Re-organize CVA6 and APU (#725)
* Initial repository re-organization (#662)

Initial attempt to split core from APU.

Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>

Compile `corev_apu` (#667)

* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

Add extended verification support (#685)

* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6

according to variant variable

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* add RVFI tracer and debug support

New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv

- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Move example_tb from cva6 to core-v-verif project

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Makefile: remove useless rule for vsim

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Makefile: add timescale definition when vsim is used

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Makefile: add vcs support (fix #570)

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* rvfi_tracer.sv: fix compilation error raised by vcs

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Makefile: use only 2 threads for verilator

when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Flist.cva6: cleanup for synthesis workflow

Thales synthesis workflow does not manage comments at end of lines

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Support FPGA generation

- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Create cva6_config_pkg to setup 32- or 64-bit configuration

According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures

needed for dc_shell

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* riscv_pkg.sv: clean-up the cva6_config_pkg import

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Add lfsr.sv to manifest

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* Directory re-organzation

* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726)

into the new file organisation

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729)

Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>

Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00

38 lines
1.4 KiB
Tcl

# Copyright 2018 ETH Zurich and University of Bologna.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
# Description: Program Genesys II
open_hw
connect_hw_server -url localhost:3121
if {$::env(BOARD) eq "genesys2"} {
open_hw_target {localhost:3121/xilinx_tcf/Digilent/200300A8CD43B}
current_hw_device [get_hw_devices xc7k325t_0]
set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7k325t_0]
program_hw_devices [get_hw_devices xc7k325t_0]
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
} elseif {$::env(BOARD) eq "vc707"} {
open_hw_target {localhost:3121/xilinx_tcf/Digilent/210203A5FC70A}
current_hw_device [get_hw_devices xc7vx485t_0]
set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7vx485t_0]
program_hw_devices [get_hw_devices xc7vx485t_0]
refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0]
} else {
exit 1
}