Florian Zaruba cb9ea12177 fpga: Fix IP synthesis for Vivado 2020.2 (#604) ... Signed-off-by: Florian Zaruba <florian@openhwgroup.org>		2021-02-08 17:51:01 +01:00
..
program.tcl	fpga: Add VC707 compatibility (#335)	2019-10-11 13:41:41 +02:00
prologue.tcl	Add System Verilog FPU (#163)	2019-03-18 11:51:58 +01:00
run.tcl	fpga: Fix IP synthesis for Vivado 2020.2 (#604)	2021-02-08 17:51:01 +01:00
write_cfgmem.tcl	fpga/kc705: Add mcs file generation (#560)	2020-12-01 14:59:58 +01:00