mirror of
https://github.com/openhwgroup/cva6.git
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107 lines
4.9 KiB
Tcl
107 lines
4.9 KiB
Tcl
# Copyright 2018 ETH Zurich and University of Bologna.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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# hard-coded to Genesys 2 for the moment
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if {$::env(BOARD) eq "genesys2"} {
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add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
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} elseif {$::env(BOARD) eq "kc705"} {
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add_files -fileset constrs_1 -norecurse constraints/kc705.xdc
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} elseif {$::env(BOARD) eq "vc707"} {
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add_files -fileset constrs_1 -norecurse constraints/vc707.xdc
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} else {
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exit 1
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}
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read_ip { \
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"xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \
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"xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci" \
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"xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci" \
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"xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci" \
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"xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci" \
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"xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci" \
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}
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# read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci
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set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
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source scripts/add_sources.tcl
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set_property top ${project}_xilinx [current_fileset]
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if {$::env(BOARD) eq "genesys2"} {
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read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
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set file "src/genesysii.svh"
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set registers "../src/common_cells/include/common_cells/registers.svh"
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} elseif {$::env(BOARD) eq "kc705"} {
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read_verilog -sv {src/kc705.svh ../src/common_cells/include/common_cells/registers.svh}
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set file "src/kc705.svh"
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set registers "../src/common_cells/include/common_cells/registers.svh"
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} elseif {$::env(BOARD) eq "vc707"} {
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read_verilog -sv {src/vc707.svh ../src/common_cells/include/common_cells/registers.svh}
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set file "src/vc707.svh"
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set registers "../src/common_cells/include/common_cells/registers.svh"
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} else {
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exit 1
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}
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
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set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
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update_compile_order -fileset sources_1
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add_files -fileset constrs_1 -norecurse constraints/$project.xdc
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synth_design -rtl -name rtl_1
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set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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exec mkdir -p reports/
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exec rm -rf reports/*
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check_timing -verbose -file reports/$project.check_timing.rpt
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report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
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report_utilization -hierarchical -file reports/$project.utilization.rpt
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report_cdc -file reports/$project.cdc.rpt
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report_clock_interaction -file reports/$project.clock_interaction.rpt
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# set for RuntimeOptimized implementation
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set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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launch_runs impl_1
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wait_on_run impl_1
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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# output Verilog netlist + SDC for timing simulation
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write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
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write_verilog -force -mode timesim work-fpga/${project}_timesim.v
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write_sdf -force work-fpga/${project}_timesim.sdf
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# reports
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exec mkdir -p reports/
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exec rm -rf reports/*
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check_timing -file reports/${project}.check_timing.rpt
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report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt
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report_utilization -hierarchical -file reports/${project}.utilization.rpt
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