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05f2a69c5f
This commit implements a very basic testbench that which reads from an instruction file and supplies the instructions upon request to the IF unit. The IF Unit is primarily the same as in RI5CY but does not implement control flow changes of any kind at the moment. It is furthermore more decoupled from the rest of the pipeline as it is done in all major processors: The processor requests instruction from the IF stage and acknowledges them. At the moment the processor only supports 64bit register register instructions, NOP and load immediate (ADDI). Results are written back by the simple commit unit.
51 lines
No EOL
1.3 KiB
Systemverilog
51 lines
No EOL
1.3 KiB
Systemverilog
/* File: commit_stage.sv
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* Author: Florian Zaruba <zarubaf@ethz.ch>
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* Date: 15.4.2017
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*
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* Copyright (C) 2017 ETH Zurich, University of Bologna
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* All rights reserved.
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*
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* Description: Commits the architectural state resulting from the scoreboard.
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*/
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import ariane_pkg::*;
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module commit_stage (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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output priv_lvl_t priv_lvl_o, // privilege level out
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output exception exception_o, // take exception to controller and if
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// from scoreboard
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input scoreboard_entry commit_instr_i,
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output logic commit_ack_o,
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// to register file
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output logic[4:0] waddr_a_o,
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output logic[63:0] wdata_a_o,
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output logic we_a_o
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);
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assign waddr_a_o = commit_instr_i.rd;
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assign wdata_a_o = commit_instr_i.result;
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// commit instruction
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always_comb begin : commit
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// default assignments
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commit_ack_o = 1'b0;
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we_a_o = 1'b0;
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if (commit_instr_i.valid) begin
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we_a_o = 1'b1;
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commit_ack_o = 1'b1;
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end
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end
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// write register file
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// CSR logic
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// privilege check
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// exception logic
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endmodule |