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https://github.com/openhwgroup/cva6.git
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First test with back to back ALU instructions
This commit implements a very basic testbench that which reads from an instruction file and supplies the instructions upon request to the IF unit. The IF Unit is primarily the same as in RI5CY but does not implement control flow changes of any kind at the moment. It is furthermore more decoupled from the rest of the pipeline as it is done in all major processors: The processor requests instruction from the IF stage and acknowledges them. At the moment the processor only supports 64bit register register instructions, NOP and load immediate (ADDI). Results are written back by the simple commit unit.
This commit is contained in:
Florian Zaruba
parent
0593615513
commit
05f2a69c5f
14 changed files with 438 additions and 117 deletions
6
Makefile
6
Makefile
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@ -5,8 +5,8 @@
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# compile everything in the following library
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library = work
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# Top level module to compile
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top_level = ariane
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test_top_level = alu_tb
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top_level = core_tb
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test_top_level = core_tb
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tests = alu scoreboard
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# path to agents
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agents = tb/agents/fu_if/fu_if.sv tb/agents/fu_if/fu_if_agent_pkg.sv \
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@ -49,7 +49,7 @@ build:
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# Run the specified test case
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sim:
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# vsim${questa_version} ${top_level}_optimized -c -do "run -a"
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vsim${questa_version} ${top_level}_optimized +UVM_TESTNAME=${test_case} -do "run -a"
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vsim${questa_version} ${top_level}_optimized +UVM_TESTNAME=${test_case}
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$(tests):
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# Optimize top level
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9
alu.sv
9
alu.sv
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@ -20,11 +20,6 @@ module alu
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input logic [63:0] operand_a_i,
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input logic [63:0] operand_b_i,
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input logic [64:0] multdiv_operand_a_i,
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input logic [64:0] multdiv_operand_b_i,
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input logic multdiv_en_i,
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output logic [63:0] adder_result_o,
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output logic [65:0] adder_result_ext_o,
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@ -75,11 +70,11 @@ module alu
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end
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// prepare operand a
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assign adder_in_a = multdiv_en_i ? multdiv_operand_a_i : {operand_a_i, 1'b1};
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assign adder_in_a = {operand_a_i, 1'b1};
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// prepare operand b
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assign operand_b_neg = {operand_b_i, 1'b0} ^ {65{adder_op_b_negate}};
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assign adder_in_b = multdiv_en_i ? multdiv_operand_b_i : operand_b_neg ;
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assign adder_in_b = operand_b_neg ;
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// actual adder
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assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
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55
ariane.sv
55
ariane.sv
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@ -45,7 +45,6 @@ module ariane
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);
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logic rst_ni;
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logic flush_i;
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// logic [31:0] instruction_i;
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// logic instruction_valid_i;
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@ -68,7 +67,6 @@ module ariane
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// synth stuff
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assign flush_i = 1'b0;
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logic req_i;
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logic if_busy_o;
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logic id_ready_i;
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logic halt_if_i;
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@ -90,27 +88,32 @@ module ariane
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logic mult_valid_i;
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priv_lvl_t priv_lvl_o;
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exception exception_o;
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scoreboard_entry commit_instr_o;
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if_stage i_if_stage (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.req_i ( req_i ),
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.if_busy_o ( if_busy_o ),
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.id_ready_i ( id_ready_i ),
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.halt_if_i ( halt_if_i ),
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.instr_req_o ( instr_if.data_req ),
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.instr_addr_o ( instr_if.address ),
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.instr_gnt_i ( instr_if.data_gnt ),
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.instr_rvalid_i ( instr_if.data_rvalid ),
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.instr_rdata_i ( instr_if.data_rdata ),
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.instr_valid_id_o ( instr_valid_id_o ),
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.instr_rdata_id_o ( instr_rdata_id_o ),
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.is_compressed_id_o ( is_compressed_id_o ),
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.illegal_c_insn_id_o ( illegal_c_insn_id_o ),
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.pc_if_o ( pc_if_o ),
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.pc_id_o ( pc_id_o ),
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.boot_addr_i ( boot_addr_i )
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);
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assign id_ready_i = 1'b1;
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assign halt_if_i = 1'b0;
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if_stage i_if_stage (
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.clk_i ( clk_i ),
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.rst_ni ( rst_n ),
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.flush_i ( 1'b0 ),
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.req_i ( fetch_enable_i ),
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.if_busy_o ( if_busy_o ),
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.id_ready_i ( id_ready_i ),
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.halt_if_i ( halt_if_i ),
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.instr_req_o ( instr_if.data_req ),
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.instr_addr_o ( instr_if.address ),
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.instr_gnt_i ( instr_if.data_gnt ),
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.instr_rvalid_i ( instr_if.data_rvalid ),
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.instr_rdata_i ( instr_if.data_rdata ),
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.instr_valid_id_o ( instr_valid_id_o ),
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.instr_rdata_id_o ( instr_rdata_id_o ),
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.is_compressed_id_o ( is_compressed_id_o ),
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.illegal_c_insn_id_o ( illegal_c_insn_id_o ),
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.pc_if_o ( pc_if_o ),
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.pc_id_o ( pc_id_o ),
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.boot_addr_i ( boot_addr_i )
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);
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id_stage
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#(
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@ -118,13 +121,13 @@ if_stage i_if_stage (
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)
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id_stage_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.rst_ni ( rst_n ),
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.test_en_i ( test_en_i ),
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.flush_i ( flush_i ),
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.instruction_i ( instr_rdata_id_o ),
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.instruction_valid_i ( instr_valid_id_o ),
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.pc_if_i ( pc_if_o ), // PC from if
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.ex_i ( ), // exception from if
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.ex_i ( '{default: 0} ), // exception from if
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.ready_o ( ready_o ),
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.operator_o ( operator_o ),
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.operand_a_o ( operand_a_o ),
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@ -150,7 +153,7 @@ if_stage i_if_stage (
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ex_stage ex_stage_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.rst_ni ( rst_n ),
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.operator_i ( operator_o ),
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.operand_a_i ( operand_a_o ),
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.operand_b_i ( operand_b_o ),
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@ -171,7 +174,7 @@ if_stage i_if_stage (
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commit_stage i_commit_stage (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.rst_ni ( rst_n ),
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.priv_lvl_o ( priv_lvl_o ),
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.exception_o ( exception_o ),
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.commit_instr_i ( commit_instr_o ),
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@ -33,7 +33,8 @@ module commit_stage (
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// commit instruction
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always_comb begin : commit
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// default assignments
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we_a_o = 1'b0;
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commit_ack_o = 1'b0;
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we_a_o = 1'b0;
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if (commit_instr_i.valid) begin
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we_a_o = 1'b1;
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commit_ack_o = 1'b1;
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11
decoder.sv
11
decoder.sv
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@ -82,15 +82,24 @@ module decoder (
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end
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OPCODE_OP32: begin
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instruction_o.fu = ALU;
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instruction_o.rs1 = instr.rtype.rs1;
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instruction_o.rs2 = instr.rtype.rs2;
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instruction_o.rd = instr.rtype.rd;
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end
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OPCODE_OPIMM: begin
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instruction_o.fu = ALU;
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imm_select = IIMM;
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instruction_o.rs1 = instr.itype.rs1;
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instruction_o.rd = instr.itype.rd;
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end
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OPCODE_OPIMM32: begin
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instruction_o.fu = ALU;
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imm_select = IIMM;
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instruction_o.rs1 = instr.itype.rs1;
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instruction_o.rd = instr.itype.rd;
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end
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OPCODE_STORE: begin
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@ -25,8 +25,8 @@ module ex_stage (
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);
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// ALU is a single cycle instructions
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assign alu_ready_o = alu_valid_i;
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// ALU is a single cycle instructions, hence it is always ready
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assign alu_ready_o = 1'b1;
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assign alu_valid_o = alu_valid_i;
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assign alu_trans_id_o = trans_id_i;
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@ -34,9 +34,6 @@ alu alu_i (
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.operator_i ( operator_i ),
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.operand_a_i ( operand_a_i ),
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.operand_b_i ( operand_b_i ),
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.multdiv_operand_a_i ( ),
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.multdiv_operand_b_i ( ),
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.multdiv_en_i ( ),
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.adder_result_o ( ),
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.adder_result_ext_o ( ),
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.result_o ( alu_result_o ),
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@ -68,7 +68,7 @@ module id_stage #(
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// TODO: Branching logic
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assign ready_o = ~full_o;
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logic illegal_instr_o;
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logic illegal_instr_o;
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decoder decoder_i (
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.clk_i ( clk_i ),
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24
if_stage.sv
24
if_stage.sv
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@ -31,6 +31,7 @@ import ariane_pkg::*;
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module if_stage (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i,
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input logic req_i, // request new instructions
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output logic if_busy_o, // is the IF stage busy fetching instructions?
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input logic id_ready_i,
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@ -65,19 +66,20 @@ module if_stage (
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// offset FSM
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enum logic[0:0] {WAIT, IDLE} offset_fsm_cs, offset_fsm_ns;
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assign pc_if_o = fetch_addr;
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// compressed instruction decoding, or more precisely compressed instruction
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// expander
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//
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// since it does not matter where we decompress instructions, we do it here
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// to ease timing closure
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logic [31:0] instr_decompressed;
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logic illegal_c_insn;
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logic instr_compressed_int;
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logic clear_instr_valid_i;
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assign pc_if_o = fetch_addr;
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// id stage acknowledged
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assign clear_instr_valid_i = id_ready_i;
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// compressed instruction decoding, or more precisely compressed instruction
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// expander
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//
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// since it does not matter where we decompress instructions, we do it here
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// to ease timing closure
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compressed_decoder compressed_decoder_i
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(
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.instr_i ( fetch_rdata ),
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@ -94,7 +96,7 @@ module if_stage (
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.req_i ( req_i ),
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.branch_i ( ), // kill everything
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.branch_i ( flush_i ), // kill everything
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.addr_i ( {fetch_addr_n[63:1], 1'b0} ),
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.ready_i ( fetch_ready ),
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@ -113,7 +115,7 @@ module if_stage (
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.busy_o ( prefetch_busy )
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);
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assign fetch_addr_n = {boot_addr_i[63:8], EXC_OFF_RST};
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assign fetch_addr_n = 64'b0; //{boot_addr_i[63:8], EXC_OFF_RST};
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// offset FSM state
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always_ff @(posedge clk_i, negedge rst_ni)
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@ -202,7 +204,7 @@ module if_stage (
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assign if_ready = valid & id_ready_i;
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assign if_valid = (~halt_if_i) & id_ready_i;
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assign if_valid = (~halt_if_i) & if_ready;
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assign if_busy_o = prefetch_busy;
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//-------------
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// Assertions
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@ -80,35 +80,35 @@ package ariane_pkg;
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// Instruction Types
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// --------------------
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typedef struct packed {
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logic [6:0] opcode;
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logic [11:7] rd;
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logic [14:12] funct3;
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logic [19:15] rs1;
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logic [24:20] rs2;
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logic [31:25] funct7;
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logic [24:20] rs2;
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logic [19:15] rs1;
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logic [14:12] funct3;
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logic [11:7] rd;
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logic [6:0] opcode;
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} rtype;
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typedef struct packed {
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logic [6:0] opcode;
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logic [11:7] rd;
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logic [14:12] funct3;
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logic [19:15] rs1;
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logic [31:20] imm;
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logic [19:15] rs1;
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logic [14:12] funct3;
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logic [11:7] rd;
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logic [6:0] opcode;
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} itype;
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typedef struct packed {
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logic [6:0] opcode;
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logic [11:7] imm0;
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logic [14:12] funct3;
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logic [19:15] rs1;
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logic [24:20] rs2;
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logic [31:25] imm1;
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logic [24:20] rs2;
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logic [19:15] rs1;
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logic [14:12] funct3;
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logic [11:7] imm0;
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logic [6:0] opcode;
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} stype;
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typedef struct packed {
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logic [6:0] opcode;
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logic [11:7] rd;
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logic [31:12] funct3;
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logic [11:7] rd;
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logic [6:0] opcode;
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} utype;
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typedef union packed {
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@ -9,30 +9,47 @@
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// Guard statement proposed by "Easier UVM" (doulos)
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`ifndef MEM_IF__SV
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`define MEM_IF__SV
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interface mem_if
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#(
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parameter int ADDRESS_SIZE = 64
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);
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logic [ADDRESS_SIZE-1:0] address; // Address for read/write request
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logic [31:0] data_wdata; // Data to be written
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logic data_req; // Requests read data
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logic data_gnt; // Request has been granted, signals can be changed as
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// soon as request has been granted
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logic data_rvalid; // Read data is valid
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logic [31:0] data_rdata; // Read data
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logic data_we; // Write enable
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logic [3:0] data_be; // Byte enable
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interface mem_if #(parameter int ADDRESS_SIZE = 64,
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parameter int DATA_WIDTH = 64 )
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(input clk);
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wire [ADDRESS_SIZE-1:0] address; // Address for read/write request
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wire [DATA_WIDTH-1:0] data_wdata; // Data to be written
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wire data_req; // Requests read data
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wire data_gnt; // Request has been granted, signals can be changed as
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// soon as request has been granted
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wire data_rvalid; // Read data is valid
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wire [DATA_WIDTH-1:0] data_rdata; // Read data
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wire data_we; // Write enable
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wire [DATA_WIDTH/8-1:0] data_be; // Byte enable
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// Memory interface configured as master
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modport Master
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(
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clocking mck @(posedge clk);
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default input #1ns output #1ns;
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input address, data_wdata, data_req, data_we, data_be;
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output data_gnt, data_rvalid, data_rdata;
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endclocking
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// Memory interface configured as slave
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clocking sck @(posedge clk);
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default input #1ns output #1ns;
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output address, data_wdata, data_req, data_we, data_be;
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input data_gnt, data_rvalid, data_rdata;
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endclocking
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clocking pck @(posedge clk);
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default input #1ns output #1ns;
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input address, data_wdata, data_req, data_we, data_be,
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data_gnt, data_rvalid, data_rdata;
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endclocking
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modport Master (
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clocking mck,
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input address, data_wdata, data_req, data_we, data_be,
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output data_gnt, data_rvalid, data_rdata
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);
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// Memory interface configured as slave
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modport Slave
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(
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modport Slave (
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clocking sck,
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output address, data_wdata, data_req, data_we, data_be,
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input data_gnt, data_rvalid, data_rdata
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);
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// modport Passive (clocking pck);
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endinterface
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`endif
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@ -57,6 +57,7 @@ module issue_read_operands (
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// output flipflop (ID <-> EX)
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logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q;
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logic alu_valid_n, alu_valid_q;
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logic [4:0] trans_id_n, trans_id_q;
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alu_op operator_n, operator_q;
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// forwarding signals
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@ -66,6 +67,7 @@ module issue_read_operands (
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assign operand_b_o = operand_b_q;
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assign operator_o = operator_q;
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assign alu_valid_o = alu_valid_q;
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assign trans_id_o = trans_id_q;
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// ---------------
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// Issue Stage
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// ---------------
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|
|
@ -158,15 +160,17 @@ module issue_read_operands (
|
|||
operand_b_n = issue_instr_i.imm;
|
||||
end
|
||||
|
||||
trans_id_n = issue_instr_i.trans_id;
|
||||
operator_n = issue_instr_i.op;
|
||||
end
|
||||
// FU select
|
||||
always_comb begin : unit_valid
|
||||
alu_valid_n = alu_valid_q;
|
||||
alu_valid_n = 1'b0;
|
||||
lsu_valid_o = 1'b0;
|
||||
mult_valid_o = 1'b0;
|
||||
// Exception pass through
|
||||
// if an exception has occurred simply pass it through
|
||||
if (~issue_instr_i.ex.valid) begin
|
||||
if (~issue_instr_i.ex.valid && issue_instr_valid_i) begin
|
||||
case (issue_instr_i.fu)
|
||||
ALU:
|
||||
alu_valid_n = 1'b1;
|
||||
|
|
@ -208,11 +212,13 @@ module issue_read_operands (
|
|||
operand_b_q <= '{default: 0};
|
||||
alu_valid_q <= 1'b0;
|
||||
operator_q <= ADD;
|
||||
trans_id_q <= 5'b0;
|
||||
end else begin
|
||||
operand_a_q <= operand_a_n;
|
||||
operand_b_q <= operand_b_n;
|
||||
alu_valid_q <= alu_valid_n;
|
||||
operator_q <= operator_n;
|
||||
trans_id_q <= trans_id_n;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -179,8 +179,9 @@ always_comb begin : issue_instruction
|
|||
|
||||
// provide a combinatorial path in case the scoreboard is empty
|
||||
if (top_pointer_q == issue_pointer_q) begin
|
||||
issue_instr_o = decoded_instr_i;
|
||||
issue_instr_valid_o = decoded_instr_valid_i;
|
||||
issue_instr_o = decoded_instr_i;
|
||||
issue_instr_o.trans_id = issue_pointer_q;
|
||||
issue_instr_valid_o = decoded_instr_valid_i;
|
||||
// if not empty go to scoreboard and get the instruction at the issue pointer
|
||||
end else begin
|
||||
issue_instr_o = mem_q[$unsigned(issue_pointer_q)];
|
||||
|
|
|
|||
|
|
@ -17,12 +17,11 @@ module core_tb;
|
|||
logic test_en_i;
|
||||
logic fetch_enable_i;
|
||||
logic core_busy_o;
|
||||
logic [-1:0] ext_perf_counters_i;
|
||||
logic [63:0] boot_addr_i;
|
||||
logic [3:0] core_id_i;
|
||||
logic [5:0] cluster_id_i;
|
||||
mem_if instr_if();
|
||||
mem_if data_if();
|
||||
mem_if #(.DATA_WIDTH(32)) instr_if(clk_i);
|
||||
mem_if data_if(clk_i);
|
||||
logic irq_i;
|
||||
logic [4:0] irq_id_i;
|
||||
logic irq_ack_o;
|
||||
|
|
@ -30,25 +29,28 @@ module core_tb;
|
|||
logic sec_lvl_o;
|
||||
debug_if debug_if();
|
||||
|
||||
ariane i_ariane (
|
||||
.clk_i (clk_i ),
|
||||
.rst_n (rst_ni ),
|
||||
.clock_en_i (clock_en_i ),
|
||||
.test_en_i (test_en_i ),
|
||||
.fetch_enable_i (fetch_enable_i ),
|
||||
.core_busy_o (core_busy_o ),
|
||||
.ext_perf_counters_i(ext_perf_counters_i),
|
||||
.boot_addr_i (boot_addr_i ),
|
||||
.core_id_i (core_id_i ),
|
||||
.cluster_id_i (cluster_id_i ),
|
||||
.instr_if (instr_if ),
|
||||
.data_if (data_if ),
|
||||
.irq_i (irq_i ),
|
||||
.irq_id_i (irq_id_i ),
|
||||
.irq_ack_o (irq_ack_o ),
|
||||
.irq_sec_i (irq_sec_i ),
|
||||
.sec_lvl_o (sec_lvl_o ),
|
||||
.debug_if (debug_if )
|
||||
assign boot_addr_i = 64'b0;
|
||||
assign test_en_i = 1'b0;
|
||||
|
||||
ariane dut (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_n ( rst_ni ),
|
||||
.clock_en_i ( clock_en_i ),
|
||||
.test_en_i ( test_en_i ),
|
||||
.fetch_enable_i ( fetch_enable_i ),
|
||||
.core_busy_o ( core_busy_o ),
|
||||
.ext_perf_counters_i ( ),
|
||||
.boot_addr_i ( boot_addr_i ),
|
||||
.core_id_i ( core_id_i ),
|
||||
.cluster_id_i ( cluster_id_i ),
|
||||
.instr_if ( instr_if ),
|
||||
.data_if ( data_if ),
|
||||
.irq_i ( irq_i ),
|
||||
.irq_id_i ( irq_id_i ),
|
||||
.irq_ack_o ( irq_ack_o ),
|
||||
.irq_sec_i ( irq_sec_i ),
|
||||
.sec_lvl_o ( sec_lvl_o ),
|
||||
.debug_if ( debug_if )
|
||||
);
|
||||
|
||||
// clock process
|
||||
|
|
@ -57,14 +59,48 @@ module core_tb;
|
|||
rst_ni = 1'b0;
|
||||
repeat(8)
|
||||
#10ns clk_i = ~clk_i;
|
||||
|
||||
rst_ni = 1'b1;
|
||||
forever
|
||||
#10ns clk_i = ~clk_i;
|
||||
end
|
||||
|
||||
program testbench (mem_if instr_if);
|
||||
initial begin
|
||||
fetch_enable_i = 1'b0;
|
||||
wait(rst_ni)
|
||||
#1ns fetch_enable_i = 1'b1;
|
||||
|
||||
end
|
||||
|
||||
program testbench (mem_if instr_if);
|
||||
logic [7:0] imem [400];
|
||||
logic [63:0] address;
|
||||
// instruction memory
|
||||
initial begin
|
||||
// read mem file
|
||||
$readmemh("add_test.v", imem, 64'b0);
|
||||
$display("Read instruction memory file");
|
||||
instr_if.mck.data_rdata <= 32'b0;
|
||||
// apply stimuli for instruction interface
|
||||
forever begin
|
||||
// instr_if.mck.data_rvalid <= 1'b0;
|
||||
instr_if.mck.data_gnt <= 1'b0;
|
||||
@(instr_if.mck iff instr_if.mck.data_req)
|
||||
// while (instr_if.mck.data_req) begin
|
||||
address <= instr_if.mck.address;
|
||||
instr_if.mck.data_gnt <= 1'b1;
|
||||
instr_if.mck.data_rvalid <= 1'b0;
|
||||
$display("Address %0h", address);
|
||||
@(instr_if.mck)
|
||||
instr_if.mck.data_rvalid <= 1'b1;
|
||||
instr_if.mck.data_rdata <= {
|
||||
imem[$unsigned(address + 3)],
|
||||
imem[$unsigned(address + 2)],
|
||||
imem[$unsigned(address + 1)],
|
||||
imem[$unsigned(address + 0)]
|
||||
};
|
||||
// end
|
||||
end
|
||||
end
|
||||
endprogram
|
||||
|
||||
testbench tb(instr_if);
|
||||
|
|
|
|||
254
wave.do
Normal file
254
wave.do
Normal file
|
|
@ -0,0 +1,254 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/clk
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/address
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_wdata
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_req
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_gnt
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_rvalid
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_rdata
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_we
|
||||
add wave -noupdate -group instr_if /core_tb/instr_if/data_be
|
||||
add wave -noupdate -group Core /core_tb/dut/clk_i
|
||||
add wave -noupdate -group Core /core_tb/dut/rst_n
|
||||
add wave -noupdate -group Core /core_tb/dut/clock_en_i
|
||||
add wave -noupdate -group Core /core_tb/dut/test_en_i
|
||||
add wave -noupdate -group Core /core_tb/dut/fetch_enable_i
|
||||
add wave -noupdate -group Core /core_tb/dut/core_busy_o
|
||||
add wave -noupdate -group Core /core_tb/dut/ext_perf_counters_i
|
||||
add wave -noupdate -group Core /core_tb/dut/boot_addr_i
|
||||
add wave -noupdate -group Core /core_tb/dut/core_id_i
|
||||
add wave -noupdate -group Core /core_tb/dut/cluster_id_i
|
||||
add wave -noupdate -group Core /core_tb/dut/irq_i
|
||||
add wave -noupdate -group Core /core_tb/dut/irq_id_i
|
||||
add wave -noupdate -group Core /core_tb/dut/irq_ack_o
|
||||
add wave -noupdate -group Core /core_tb/dut/irq_sec_i
|
||||
add wave -noupdate -group Core /core_tb/dut/sec_lvl_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/clk_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/rst_ni
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/req_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/if_busy_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/id_ready_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/halt_if_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_req_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_addr_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_gnt_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rvalid_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rdata_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_valid_id_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rdata_id_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/is_compressed_id_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/illegal_c_insn_id_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/pc_if_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/pc_id_o
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/boot_addr_i
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/if_ready
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/if_valid
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/branch_req
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/valid
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/prefetch_busy
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_addr_n
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_valid
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_ready
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_rdata
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_addr
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/offset_fsm_cs
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/offset_fsm_ns
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_decompressed
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/illegal_c_insn
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_compressed_int
|
||||
add wave -noupdate -group if /core_tb/dut/i_if_stage/clear_instr_valid_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/clk
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/rst_n
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/req_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/branch_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/ready_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/valid_o
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_o
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/rdata_o
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_req_o
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_gnt_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_addr_o
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_rdata_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_rvalid_i
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/busy_o
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/CS
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/NS
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_addr_q
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fetch_addr
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_valid
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_valid
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_ready
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_clear
|
||||
add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/valid_stored
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/clk_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rst_ni
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/test_en_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/flush_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/instruction_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/instruction_valid_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/pc_if_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/ex_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/ready_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operator_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operand_a_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operand_b_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/trans_id_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/alu_ready_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/alu_valid_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/lsu_ready_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/lsu_valid_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/mult_ready_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/mult_valid_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/trans_id_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wdata_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wb_valid_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/waddr_a_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wdata_a_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/we_a_i
|
||||
add wave -noupdate -expand -group id_stage -expand /core_tb/dut/id_stage_i/commit_instr_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/commit_ack_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/full_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rd_clobber_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_valid_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_valid_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_instr_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/decoded_instr_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_instr_valid_o
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_ack_i
|
||||
add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/illegal_instr_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/clk_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/rst_ni
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operator_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operand_a_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operand_b_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/trans_id_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_ready_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_result_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_trans_id_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/comparison_result_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/lsu_ready_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/lsu_valid_i
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/mult_ready_o
|
||||
add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/mult_valid_i
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/clk_i
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/rst_ni
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/pc_i
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_i
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/ex_i
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_o
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/illegal_instr_o
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instr
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_select
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_i_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_iz_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_sb_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_u_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_uj_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_z_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s2_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_bi_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s3_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vs_type
|
||||
add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vu_type
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operator_i
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_i
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_i
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_o
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_ext_o
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/result_o
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/comparison_result_o
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal_result_o
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev32
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_neg
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_op_b_negate
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_a
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_b
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_arithmetic
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_amt
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a32
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result32
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result32
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result32
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_64
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_32
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_greater_equal
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_signed
|
||||
add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_result
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/clk_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rst_ni
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/test_en_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/flush_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_valid_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_ack_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_valid_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_valid_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rd_clobber_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_ready_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_ready_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_valid_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_ready_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_valid_o
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/waddr_a_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/wdata_a_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/we_a_i
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/stall
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/fu_busy
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_regfile
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_regfile
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_n
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_q
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_n
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_q
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_n
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_q
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_n
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_q
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_n
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_q
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs1
|
||||
add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs2
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {499 ns} 0} {{Cursor 2} {278 ns} 1}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 241
|
||||
configure wave -valuecolwidth 258
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {840 ns}
|
||||
Loading…
Add table
Add a link
Reference in a new issue