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cache_subsystem
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[Bugfix hpdcache] axi struct usage (#1802)
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2024-02-05 18:51:44 +01:00 |
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cvxif_example
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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frontend
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port_builder generates the table of ports (#1805)
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2024-02-06 12:06:13 +01:00 |
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include
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Configure icache with 2 ways in cv32a65x (#1800)
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2024-02-01 16:47:05 +01:00 |
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mmu_sv32
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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mmu_sv39
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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pmp
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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acc_dispatcher.sv
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acc_dispatcher: Add ld/st priv mode, sum & PMP iface (#1767)
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2024-01-17 00:43:21 +01:00 |
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alu.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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amo_buffer.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile_ff.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile_fpga.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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axi_shim.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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branch_unit.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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commit_stage.sv
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Modify coding style to improve CC (#1642)
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2023-11-21 19:04:55 +01:00 |
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compressed_decoder.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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controller.sv
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Modify coding style to improve CC (#1642)
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2023-11-21 19:04:55 +01:00 |
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csr_buffer.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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csr_regfile.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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cva6.sv
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port_builder generates the table of ports (#1805)
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2024-02-06 12:06:13 +01:00 |
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cva6_accel_first_pass_decoder_stub.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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cva6_rvfi.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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cva6_rvfi_probes.sv
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Remove all logic and sequential related to RVFI in CORE cva6 (#1762)
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2024-01-18 22:51:10 +01:00 |
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cvxif_fu.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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decoder.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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ex_stage.sv
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Remove all logic and sequential related to RVFI in CORE cva6 (#1762)
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2024-01-18 22:51:10 +01:00 |
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Flist.cva6
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Remove all logic and sequential related to RVFI in CORE cva6 (#1762)
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2024-01-18 22:51:10 +01:00 |
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Flist.cva6_gate
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Parametrize debug module (#1382)
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2023-09-13 16:22:24 +02:00 |
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fpu_wrap.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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id_stage.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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instr_realign.sv
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port_builder generates the table of ports (#1805)
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2024-02-06 12:06:13 +01:00 |
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issue_read_operands.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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issue_stage.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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load_store_unit.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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load_unit.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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lsu_bypass.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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mult.sv
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Code coverage: condition RTL With parameters (#1703)
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2023-12-13 07:52:47 +01:00 |
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multiplier.sv
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csr_regfile.sv: add RVB field for MISA (fix #1734) (#1760)
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2024-01-15 14:34:25 +01:00 |
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perf_counters.sv
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Fix event tracing on more commit ports. (#1665)
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2023-12-06 11:49:32 +01:00 |
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scoreboard.sv
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Parameterize TVAL to reduce size in embedded (#1784)
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2024-01-25 15:47:06 +01:00 |
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serdiv.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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store_buffer.sv
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Remove all logic and sequential related to RVFI in CORE cva6 (#1762)
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2024-01-18 22:51:10 +01:00 |
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store_unit.sv
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Remove all logic and sequential related to RVFI in CORE cva6 (#1762)
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2024-01-18 22:51:10 +01:00 |
