mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-21 12:47:11 -04:00
8468544156
* Fix latch and timing loop in debu_req * Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE * Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data * Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode. * Initialize instruction traced shadow regfile to zero at start of simulation Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X Fix printouts of assertions Modify bootrom to prevent assignment of X to output * Make separate CI target for AMO tests * Bump fpga-support version * Add AMO tests list * Fix FPU submodule version * Change core_id + cluster_id into hart_id * Rename gitlab CI tests * Replace all SYNTHESIS macros with pragma translate_off * Update readme, bump common cells, benderize * Fix torture make target * Remove unneeded signal
22 lines
688 B
Bash
22 lines
688 B
Bash
# Customise this to a fast local disk
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export TOP=/scratch/$USER/projects
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export CI_BUILD_DIR=$TOP/ariane-repo
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#customize this to your setup
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export QUESTASIM_HOME=
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export QUESTASIM_VERSION=
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export QUESTASIM_FLAGS=-noautoldlibpath
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export CXX=g++-7 CC=gcc-7
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# where to install the tools
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export RISCV=$TOP/riscv_install
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export VERILATOR_ROOT=$TOP/verilator-3.924/
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export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
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export LIBRARY_PATH=$RISCV/lib
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export LD_LIBRARY_PATH=$RISCV/lib
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export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
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export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
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# number of parallel jobs to use for make commands and simulation
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export NUM_JOBS=8
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