mirror of
https://github.com/openhwgroup/cva6.git
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b1bdc0c02c
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
22 lines
No EOL
671 B
Bash
22 lines
No EOL
671 B
Bash
# Customise this to a fast local disk
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export TOP=/scratch/$USER/projects
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export CI_BUILD_DIR=$TOP/ariane-repo
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#customize this to your setup
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export QUESTASIM_HOME=
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export QUESTASIM_VERSION=
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export QUESTASIM_FLAGS=
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export CXX=g++-7 CC=gcc-7
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# where to install the tools
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export RISCV=$TOP/riscv_install
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export VERILATOR_ROOT=$TOP/verilator-4.008/
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export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
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export LIBRARY_PATH=$RISCV/lib
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export LD_LIBRARY_PATH=$RISCV/lib
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export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
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export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
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# number of parallel jobs to use for make commands and simulation
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export NUM_JOBS=8 |