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cva6/fpga
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Florian Zaruba ad223cfd9f Clean-up naming to distinguish OP from GP Ariane (#193) 
* Clean-up naming to distinguish  OP from GP Ariane

* Rename wb to wt in hidden CI files

* Fix verilator install script
2019-03-18 11:51:58 +01:00
..
constraints Improve Tandem Simulation, switch-able caches and fix a cache-bug (#192) 2019-03-18 11:51:58 +01:00
scripts Improve Tandem Simulation, switch-able caches and fix a cache-bug (#192) 2019-03-18 11:51:58 +01:00
src Clean-up naming to distinguish OP from GP Ariane (#193) 2019-03-18 11:51:58 +01:00
xilinx Improve Tandem Simulation, switch-able caches and fix a cache-bug (#192) 2019-03-18 11:51:58 +01:00
.gitignore Put batch flow in place (incl small flow fixes) 2018-11-19 19:24:31 +01:00
ariane.cfg Rerouting RISC-V DTM JTAG from PMOD header to 2nd channel of FTDI chip. 2019-01-30 11:36:34 +01:00
ariane_pmod.cfg Rerouting RISC-V DTM JTAG from PMOD header to 2nd channel of FTDI chip. 2019-01-30 11:36:34 +01:00
ariane_pmod_tiny.cfg Rerouting RISC-V DTM JTAG from PMOD header to 2nd channel of FTDI chip. 2019-01-30 11:36:34 +01:00
Makefile Adapt rgmii ethernet core from Alex Forencich for Ariane on Genesys2 2019-01-23 13:53:50 +00:00
sourceme.sh Ethernet preparation, fpga fixes 2018-11-20 19:02:52 +01:00